3.3.1 Supply Voltage Scaling
In a given technology, supply voltage reduction is the key to low power operation [23][24].
When lowering the supply voltage, there are two issues that must be considered:
1. Impact on delay: Since both capacitance and threshold voltage are constant, the speed of the basic gates will also decrease with the voltage scaling, where the relation between time delay Tdand supply voltage VDD can be modeled by using a quadratic model:
Td= k CLVDD
(VDD − VT)2 (3.11)
2. Impact on stability: Low supply voltage circuits are very sensitive to both manu-facturing variations and operating point changes, which leads to less stable and less robust operation.
Following is an example of supply voltage scaling. Figure 3.6 shows an inverter chain composed of four inverters. Figure 3.7 shows the relation between power and supply voltage; Figure 3.8 shows the relation between time delay and supply voltage. It is revealed that as supply voltage drops, power consumption is reduced, but the time delay is increased. A common vector for finding the optimal supply voltage is the power delay product (PDP), which is the product of power and time delay, as shown in Figure 3.9.
Another strategy is to find the worst case critical time delay and choose the minimum supply voltage that is capable of performing the expected operation speed.
Figure 3.6: A CMOS inverter chain.
Figure 3.7: Power versus supply voltage.
Figure 3.8: Time delay versus supply voltage.
Figure 3.9: PDP versus supply voltage.
Figure 3.10: Noise margin versus supply voltage.
Relation between noise margin [25] and supply voltage is shown in Figure 3.10. As shown, noise margin decreases as supply voltage drops. Noise margin issue is especially important in ultra-low voltage and subthreshold circuit designs [26].
3.3.2 Transistor Stacking
Transistor stacking is an effective technique to reduce subthreshold and gate leakage current [27][28]. Leakage current flowing through a stack of series-connected transistors reduces if more than one transistor in the stack is off, which is known as the stacking effect. The staking effect can be understood by considering a two-input NAND gate, as shown in Figure 3.11. When both MN1 and MN2 are off, the voltage at the intermediate node (VM) raises to a positive value due to a small drain current. Positive potential at the intermediate node leads to three effects:
1. Gate-to-source voltage of MN1 becomes negative.
2. Negative body-to-source potential of MN1 causes more body effect. The body effect describes how the potential difference between source and body affects the threshold voltage, which can be modeled as:
VT = VT 0+ γ(p
φs+ VSB−p
φs) (3.12)
where VT 0 is the threshold voltage when the source is at the body potential; φs is the surface potential at threshold, and γ is the body effect coefficient.
3. Drain-to-source potential of MN1 decreases, resulting in less drain-induced barrier lowering.
As a result, negative gate-to-source voltage, higher threshold voltage due to the body effect, and less drain-induced barrier lowering due to the reduction of drain-to-source voltage, leakage current is reduced.
Figure 3.11: Two-input NAND gate stacking effect illustration.
Transistor stacking for low power can be referred to power gating. Power gating de-vices can be classified into two main categories: footer and header dede-vices. Footer is by inserting NMOS sleep transistors between real GND and virtual GND, while header is by inserting PMOS sleep transistors between read VDD and virtual VDD, as shown in Figure 3.12 and Figure 3.13, respectively.
Figure 3.14 and Figure 3.15 are testing examples of footer and header. The effective-ness of standby power saving by footer and header are shown in Figure 3.16 and Figure 3.17. Time delay comparisons are shown in Figure 3.18 and Figure 3.19. As shown, by sacrificing operation speed, a circuit with power gating devices has significant standby power (leakage power) reduction. Trade off between power and speed is also illustrated.
For a circuit with power gating, the less power gating are inserted, the more power is saved, and the more power gating are inserted, the less time delay it performs. Adding power gating devices usually contributes very slight active power overhead, which is re-vealed in Figure 3.20 and Figure 3.21. Another interesting thing worth notice is the comparison between footer and header, which is demonstrated in Figure 3.22 and Figure 3.23. NMOS has stronger driving ability than PMOS, resulting in smaller time delay when applying footer power gating. On the other hand, as shown in Figure 3.5, PMOS has smaller leakage current than NMOS, resulting in smaller power consumption when applying header power gating.
Figure 3.12: NMOS footer array power gating devices.
Figure 3.13: PMOS header array power gating devices.
Figure 3.14: Inverter chain with footer power gating.
Figure 3.15: Inverter chain with header power gating.
Figure 3.16: Standby power comparisons when applying footer power gating.
Figure 3.17: Standby power comparisons when applying header power gating.
Figure 3.18: Time delay comparisons when applying footer power gating.
Figure 3.19: Time delay comparisons when applying header power gating.
Figure 3.20: Active power comparisons when applying footer power gating.
Figure 3.21: Active power comparisons when applying header power gating.
Figure 3.22: Time delay comparisons between footer and header. One footer/header is applied on four inverters.
Figure 3.23: Standby power comparisons between footer and header. One footer/header is applied on four inverters.
3.3.3 Multiple Threshold Designs
Multiple threshold CMOS (MTCMOS) circuit has transistors with different threshold voltage. In general, there are regular threshold (regular-VT) transistors, low threshold (low-VT) transistors, and high threshold (high-VT) transistors. Low-VT transistors has larger driving ability, and can be used to achieve high performance, but it has the largest leakage current among the three types of transistors. High-VT transistors has the least leakage current, but its performance is the slowest among the three types of transistors.
The performance of regular-VT transistors is in between low-VT and high-VT transistors.
Following are three multiple threshold technologies:
1. Dual threshold CMOS: In a logic circuit, if a logic gate is in the critical path, the gate is implemented by low-VT transistors to maintain performance; if a logic gate is in a non-critical path, the gate is implemented by high-VT transistors for leakage power reduction [29]. This technique is demonstrated in Figure 3.24.
2. Mixed-VT (MVT) CMOS technique: Unlike dual threshold CMOS technique, MVT CMOS design technique allows different thresholds within a logic gate, placing high-VT transistors in non-critical paths to reduce leakage power, and placing low-VT transistors in critical path(s) to maintain performance [30][31]. Figure 3.25 is an example of MVT CMOS logic gate. Suppose that the transistors in squares are the transistors in the critical paths, thus, assigning low-VT. For the other transistors, high-VT are assigned for leakage power reduction without degrading performance.
without delay and area overhead.
3. Multithreshold-voltage CMOS: Multithreshold-voltage CMOS (MTCMOS) tech-nique is based on transistor stacking techtech-nique, but utilizes low-VT transistors for logic gates and apply high-VT transistors to power gating [32]. Examples are shown in Figure 3.26 and Figure 3.27. Assigning high-VT to power gating devices can further improve leakage cut off efficiency, while the delay overhead can be compen-sated by low-VT logic gates. Figure 3.28 and Figure 3.29 are testing examples of MTCMOS circuit. Figure 3.30 and Figure 3.31 show the standby power compar-ison between inverter chain with and without MTCMOS technique. It is obvious MTCMOS technique significantly reduces standby power. Figure 3.32 and Fig-ure 3.33 show the time delay comparison between inverter chain with and without MTCMOS technique. High-VT has smaller driving current, thus resulting delay overhead. Delay overhead can be reduced by replacing regular-VT transistors with low-VT transistors. Figure 3.34 and Figure 3.35 show the active power compari-son between inverter chain with and without MTCMOS technique. Active power reduction by MTCMOS is not apparent in this case, since the gate count under simulation is very limited.
Figure 3.24: Dual threshold CMOS circuit.
Figure 3.25: MVT CMOS scheme.
Figure 3.26: Footer insertion MTCMOS circuit.
Figure 3.27: Header insertion MTCMOS circuit.
Figure 3.28: MTCMOS inverter chain with footer power gating.
Figure 3.29: MTCMOS inverter chain with header power gating.
Figure 3.30: Standby power comparisons when applying footer insertion MTCMOS cir-cuit.
Figure 3.31: Standby power comparisons when applying header insertion MTCMOS cir-cuit.
Figure 3.32: Time delay comparisons when applying footer insertion MTCMOS circuit.
Figure 3.33: Time delay comparisons when applying header insertion MTCMOS circuit.
Figure 3.34: Active power comparisons when applying footer insertion MTCMOS circuit.
Figure 3.35: Active power comparisons when applying header insertion MTCMOS circuit.
3.4 Summary
In this chapter, power dissipation is first reviewed, including dynamic dissipation, leakage dissipation, and short circuit dissipation. After analyzing power dissipation sources, some useful low power techniques are presented, including supply voltage scaling, transistor stacking, and multiple threshold design. Testing examples and simulation results are demonstrated, which shows the effectiveness of applying these low power techniques. All simulations done in this chapter is based on UMC 90nm CMOS technology.