Chapter 1 Introduction
1.2 Motivation
The rapid advance of integrated circuit technology has moved the minimum feature size into nanometer region. In the nano-device generation, the reliability and performances of CMOS have suffered some problems which about gate-leakage and poly depletion. In order to improve these problems, it is a tendency to choose new materials. Metal/high-k gate stack technology is a promising structure since it provides both low gate-leakage and minimal poly depletion effect [14]. Although Metal/high-k gate stack technology will be the mainstream technology in the future, as shown in Fig.1.2, there are still some drawbacks need to be overcome. The one of these is thermal reliability for high-k dielectric.
Hf-silicate which is the most plausible near-term candidate for high-k dielectric. However, it can not tolerate high temperature process, because that high-k dielectric will crystallize under high temperature process. With the high-k dielectric crystallization, the gate-leakage current will increase dramatically. Since the thermal reliability is playing an important role for Metal/high-k gate stack technology, it is why that NiSi will be chosen to the metal gate material. NiSi attributed to the low temperature process window.
However, it needs high temperature annealing to achieve high implanted dopant activation in the S/D region when adapted gate first (self-aligned) process. The threshold voltage (Vt) adjustment in the gate region also needs high level dopant activation (high thermal budgut).
In parallel with the gate dielectric engineering to improve the high-k dielectric‘s thermal reliability, we are interesting in the project about low temperature activation. If the process temperature after gate dielectric formation can be lowered, the high-k dielectric crystallized problem in process integration can also be minimized. We combined the concept of implant into silicide (IIS) and solid phase epitaxial regrowth (SPER) to lowering the process temperature. These two methods lower the dopant activation temperature through the concept of change the surface energy of silicon and pile up the dopant concentration by dopant segregation (IIS) and/or higher the solubility of the dopant in Si through the Si re-crystallization process. Details about these two methods with our experiment will be discussed in the following chapters.
1.3 Organization of the Thesis
In this thesis, we concentrate our efforts on the activation of B and P implant through silicide by RTA process. In chapter 1, brief introduction metal-silicide technology history evolution and the motivation of this thesis are mentioned. In chapter 2, find the optimized recipe to forming nickel monosilicde. In chapter 3, first overview of metal-silicide technology is given to describe the various applications and process technologies. Second the process flow of fabrication will be described. In chapter 4, the detail
discussion of characteristics includes physical properties, electrical properties and doping concentration extraction. In chapter 5 is conclusions and chapter 6 is future works.
1.4 References
[1] Anne Lauwers, An Steegen Muriel de Potter, Richard Lindsay, Alessandra Satta, Hugo Bender, and K. Maex, American Vacuum Society B 19(6) (2001).
[2] T.B. Massalski, Binary Alloy Phase Diagram, ASM international, Materials Park, OH (1990)
[3] J.C. Barbour, A.E.M.J. Fischer and J.F. van der Veen, J.Appl. Phys. 62, 2582(1987)
[4] R. Beyers and R. Sinclair, J.Appl. Phys. 57, 5240(1985)
[5] J.B. Lasky, J. S. Nakos, O. J. Cain, and P. J. Geiss, IEEE Trans, Electron Device 38, 262 (1991).
[6] K. Maex, Mater. Sci, Eng. R11, 53 (1993).
[7] J.B. Lasky, J.S. Nakos, O.J. Cain and P.J. Geiss, IEDM Trans. Electron Devices, ED-3458, 262(1991)
[8] B. S. Chen, and M. C. Chen, “Formation of Cobalt silicided Shallow Junction Using Implant Into/Through Silicate Technology and Low Temperature Furnace Annealing,” IEEE Trans.Electron Devices, vol. 43, no. 2, pp. 258-266, Feb. (1996).
[9] K. Goto, J. Watanabe, T. Sukegawa, A. Fushida, T. Sakuma, and T. Sugii,
“A Comparative Study of Leakage Mechanism of Co and Ni Salicide Processes,” IEEE Annual International eliability Physics Symposium, pp.
363-369, (1998).
[10] M.Y. Lee, P.A. Bennett, Phya. Rev. Lett. 75-4460(1995)
[11]C.A. Londos, K. Eftaxias, V. Hadjicontis, Phya. Stat. Sol.
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[12]O. Madelung, Semiconductors Basic Data, Springer, 1996
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[14]C. Hobbs et al., Symp. VLSI Tech., 9, (2003)
Chapter 2
Formation of nickel silicide
2.1 Introduction
With the lower formation temperature and lower silicon consumption, nickel silicide overcomes some limitations of cobalt silicide,and provides a scaling ability to push the device into the 30 nm technology range. For successful process integration, key material feathers and formation limitations need to be understood to minimize adverse effects on the electrical characteristics of device. A two step RTA process was shown to provide an optimal integration of NiSi technology [1]. Under the two step process, in this chapter, we would compare the sheet resistance of silicide on crystal silicon by different Ni deposition system, and select the better one as our starting deposition source in the following experiments. Also, as being a metal gate material, we compared the silicide sheet resistance formed on different a-Si source. Four point probe was adapted to measure the sheet resistance, SEM cross-sectional image would be inspected the silicide thickness, and using AFM to compare silicide roughness.
2.2 Sheet resistance test
Before the experiment begins, determining the best recipes for silicide formation is necessary. First of all, the Ni deposition source must be decided.
P-type (100) oriented Si wafers was prepared for the silicide formation substrate. After a standard RCA clean process, we deposited Ni 20 nm with Dual E-Gun Evaporation System and Sputtering System respectively. Both samples were then rapid thermal annealed (RTA) at 350℃/400℃ with different time duration in N2 ambient to form nickel silicide, the recipes listed in Table.2.1. The unreacted Ni film was selectively etched using SPM solution of (H2SO4 : H2O2 = 3 : 1) at 75~85 for ℃ 45 sec. The sheet resistance measurement results of the remaining silicide were shown in Fig.2.1. Then, we chosen the temperature which in the NiSi formation process window, 550℃ 50sec, as a second RTA process temperature [2], the sheet resistance was shown in Fig.2.2. From the results of Fig.2.1 and Fig.2.2, it shows that the lower sheet resistance of nickel silicide is the nickel deposited with the Dual E-Gun Evaporation System so that the Ni deposition for following experiment was decided by using Dual E-Gun Evaporation System.
Moreover, based on the result of Fig.2.1, it shows that the sheet resistance for the samples annealed at 350℃ was higher than those annealed at 400℃.
It is because that 350℃ is not enough to forming NiSi completely, but it can be utilized by second RTA process to transform the silicide from Ni2Si to NiSi. The second RTA process can lower sheet resistance effectively. In addition, excessive silicidation also must be concerned because it was found that the junction leakage measured on diode structures consisting of a large number of small active area islands [3,4] was greatly impoved by a reduction
of the first RTA thermal budget. As a result, the excessive silicidationcan can be reduced in a 2-step Ni-silicide process with reducing the thermal budget of the first RTA step. From the above mention, we would use 350℃
30 sec for the first step RTA being the experiment recipe.
In order to fabricate the fully silicide gate stack MOS capacitor structure, we will test the sheet resistance which use different a-Si source to react with Ni. A 300 nm oxide was thermally grown on the p-type (100) oriented Si wafer, and following a 50 nm thick a-Si was deposited using PECVD and HDPCVD, respectively. After a standard RCA clean process, 20 nm nickel was deposited using Dual E-Gun Evaporation System. Samples were then rapid thermal annealed (RTA) at 350℃ for different time duration in N2 ambient to form nickel silicide, the recipes listed in Table.2.2. The unreacted Ni film was selectively etched using a solution of H2SO4 : H2O2 = 3 : 1 at 75~85 ℃ for 45 sec. The results were shown in Fig.2.3(a). Then, we chosen the temperature which in the NiSi formation process window, 550℃ 50sec, as a second RTA process temperature, as shown in Fig.2.3(b). From the results of Fig.2.3(a) and Fig.2.3(b), the lower sheet resistance of nickel silicide is formed by the PECVD System so that the a-Si deposition which was used for fully silicide gate material.
2.3 SEM cross sectional view inspection
In order to identify the real thickness of the as-deposited Ni film and the NiSi layer formed, scanning electron microscope (SEM) was used for cross sectional view inspection. Fig.2.4 and Fig.2.5 shows SEM images of NiSi
layer formed by RTP annealing at 350 for ℃ different Ni deposition source by Dual E-Gun Evaporation System and Sputtering System, respectively.
The SEM image of silicide formed for gate stack technology was shown in Fig.2.6, it is formed by PECVD deposited a-Si with Dual E-Gun Evaporation System deposited Ni.
2.4 References
[1] John Foggiato, Woo Sik Yoo, Michel Ouaknine, Tomomi Murakami, Takahashi Fukada, Materials Science and Engineering B 114-115, 56-60(2004)
[2] F. Deng, R. A. Jihnson, P. M. Asbeck, S. S. Lau, W. B. Dubbelday, T.
Hsiao, and J. Woo, J.Appl.Phys. 81, 8047(1997)
[3] Anne Lauwers, Jorge A. Kittl, Mark J.H. Van Dal, Oxana Chamirian, Malgorzata A. Pawlak, Muriel de Potter, Richard Lindsay, Toon Raymakers, Xavier Pages, Bencherki Mebarki, Tushar Mandrekar, Karen Maex, Materials Science and Engineering B 114-115(2004)
[4] A. Lauwers, J.A. Kittl, M. Van Dal, O. Chamirian, R. Lindsay, M.
dePotter, C. Demeurisse, C. Vrancken, K. Maex, X. Pages, K. Van derJeugd, V. Kuznetsov, R. Granneman, Microelectron. Eng., accepted for publication.
Chapter 3
Characterization of Boron/Phosphorous Implanted To Silicide by Subsequence Thermal Process
3.1 Introduction
As device dimension is scaled down to deep submicron, not only the size of gate electrode is shrunk, but also the vertical dimension of doped source/drain regions must be scaled to avoid device punch through and short channel effects. In the past, PN junctions were formed by dopant ion implantation into Si substrate followed by high temperature furnace annealing for dopant activation and implantation damage annihilation.
However, channeling effect and high temperature dopant diffusion limit the formation of shallow junction. This is particularly important for the p+n junction because boron is a light element and diffuses fast in silicon. In recent years, many advanced junction formation techniques have been studied using low energy ion implantation, low temperature annealing, and rapid thermal annealing process. These new methods are briefly reviewed as follows :
(1) Pre-amorphization of silicon substrate before dopant implantation
Pre-amorphization has been widely used to control the channeling behavior of implanted dopant atoms. After the pre-amorphization of the silicon substrate surface layer, dopant implantation was performed followed
by crystal regrowth and annealing process for the junction formation. Many heavy atoms have been used as pre-amorphization species, such as Si [1] and Ge. [2-3] Solid phase epitaxial (SPE) scheme can be used to regrow the crystal from the amorphous layer at a temperature as low as 550 ℃ [4]. The growth rate depends on the element used for pre-amorphization as well as the dopant implanted following the pre-amorphization. A careful annealing process is needed to annihilate the massive defects and dislocation induced by the pre-amorphization.
(2) Elevated source/drain structure
This method is to raise the source/drain regions by depositing a polysilicon (poly-Si) or amorphous silicon (α-Si) film or growing a selective epitaxial Si or SiGe layer[5-6]. Deposition of poly-Si/α-Si film on the source/drain regions needs an additional lithographic step to define the elevated regions, while the selective epitaxial growth of silicon on the source/drain regions does not need such an additional lithographic step. The elevated source/drain regions made with selective epitaxial growth (SEG) provide a sacrificial layer for silicide formation and an alternative
approach for the salicide process. However, the SEG scheme needs a high deposition temperature to obtain good crystallinity in the epitaxial layer. The fact that high temperature process deteriorates the device performance is the main disadvantage of this method[7].
(3) Low energy ion implantation [8-10]
This is an extension of the conventional ion implantation technique. The implantation energy is lower than 1 keV and the implantation dose is typically from 1×1014 to 5×1014 cm-2. The major disadvantage of this method
is that no commercial implantation system of such a low energy ion beam is available for high throughput mass production with reasonable cost.
(4) IIS/ITM technique
The implant into silicide (IIS) and implant through metal (ITM) processes have been investigated for shallow junction formation. The IIS/ITM process consists of implanting dopants into/through silicide or metal layer and the subsequent thermal annealing to form a silicide-contacted shallow junction [11-14]. The IIS scheme in particular is of much benefit to the formation of shallow junction. This is because metal silicides have a larger nuclear stopping power than silicon for the implanted dopant ions and thus can reduce the channeling effect; in addition, the junction formed by the IIS scheme can be almost free of implant damage, which is mostly confined in the silicide layer. Thus, the post-implant annealing temperature can be lowered while shallow junctions with superb characteristics can be obtained.
Moreover, the silicided junction is conformal to the silicide/silicon interface, and thus the possibility of junction penetration by the silicide is reduced.
The need for high-activation, diffusionless junctions and low temperature process for advanced gate stacks have promoted further research in shallow junction formation. Because solid phase epitaxial regrowth(SPER)[15-17]
works on the principle that dopants in an amorphous region will activate to a level above the equilibrium solid solubility during crystalline regrowth.
Temperature even below 600℃ allow regrowth, and thus activation, with negligible dopant diffusion[18]. In this thesis, we would combine the dopant pile-up characteristic of IIS at interface and the ability of SPER to achieving the formation of N+/P and P+/N shallow junction.
3.2 Experiment
Because the experiment will need to remove the NiSi to measuring the sheet resistance which could obtain the silicide/Si interface dopant activation, we had to get the silicide etched solvent(HNO3 : NH4F : H2O= 4 : 1 : 50 ) selectivity of silicide to Si. We prepared the p-type (100) oriented Si wafers to form the NiSi and then used SEM to measure the silicide thickness was around 20nm which as shown in Fig.2.5. Before silicide etching test, we measured the sheet resistance of p-type (100) wafer and had formed silicide wafer by four-point probe. Then, we used the silicide removed solvent to etch silicide and took the duration which sheet resistance value up to the p-type (100) wafer value to be the silicide complete removed duration, 60sec.
We took the silicide removed solvent to etched p-type (100) wafer for 30min and inspected the etched thickness by AFM, as shown in Fig.3.1 to obtaining the etching rate of silicide removed solvent to p-type (100) wafer. From the experiment, we got the etching selectivity of NiSi/Si substrate was 100 : 1.
In the follow-up experiment, we would take the over etching time for 30s to conform the silicide removed completely because of the high etching selectivity.
The sheet resistance experiment samples for the four-point probe measuring structure included experimental and comparison samples. First, experimental and comparison samples were fabricated on p-type/n-type (100) oriented Si wafers. After a standard RCA clean process. Then, a 350 nm isolation oxide was grown on the wafer by wet oxidation at 1000℃ for 35 min. The active regions were defined by the photolithography and etched by BOE (buffered oxide etchant) solution. Then, experimental samples were standard cleaned again to fully remove the contamination.
Following, a 20 nm Ni deposited on the wafer in a Dual E-Gun Evaporation system with a base pressure of less than 5×10-6 torr, using a Ni target in vacuum ambient with a deposition rate of about 0.7- 1.0 Å/sec.
After the Ni film deposition, the samples were rapid thermal annealed (RTA) at 350℃ for 30 sec in N2 ambient to form NiSi. The unreacted Ni film was selectively etched using a solution of H2SO4 : H2O2 = 3 : 1 at 75~85 ℃ for 45 sec. Then, the sample of NiSi were implanted with BF2+ / P+ ions at an energy of 50 and 30 keV to a dose of 5×1015cm-2. After ion implantation, followed by rapid thermal anneal (RTA) at 400 to 650℃ for 30 / 60 sec in N2 ambient for the activation dopant, as shown in Fig.3.2.
Process recipe is listed in Table.3.1. Because the selectivity of silicide to Si is large enough, NiSi was removed by silicide etched solvent(HNO3 : NH4F : H2O= 4 : 1 : 50 ) for 90sec that included overetching 20sec. After above process, the samples were coated the Al 500nm by thermal coater, and used photolithography to define the four-point probe measuring pads.
Comparison samples were also standard cleaned again to fully remove the contamination. Following, a 20 nm screen oxide was grown on the wafer by dry oxidation at 950℃ for 30 min. Then, the sample were implanted with BF2+ / P+ ions at an energy of 28 and 43 keV to a dose of 5×1015cm-2. After ion implantation, first, removed screen oxide by BOE and following by rapid thermal anneal (RTA) at 600 to 950℃ for 30 / 60 sec in N2
ambient for the activation dopant, as shown in Fig.3.3. Process recipe is listed in Table.3.2. After above process, the samples were coated the Al 500nm by thermal coater, and used photolithography to define the four-point probe measuring pads. The last step is sintering for 400℃
10min by furnace for both experimental and comparison samples.
We would also prepare the P+/N and N+/P junction samples of silicide contact for I-V and C-V electrical properties measurement. The samples prepared steps were the same as the above mentioned experimental samples.
The different step with the experimental samples was we had not to remove silicde contact and needed to coat Al 500nm at backside. The fabricated process was shown in Fig.3.4 and process recipe is listed in Table.3.1 with the 2nd RTA duration is only 60s.
3.3 References
[1] M. H. Juang and H. C. Cheng, Appl. Phys. Lett. 60, 2092, (1992).
[2] M. C. Ozturk, J. J. Wortman, C. M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W.-K. Chu, and C. Lee, IEEE Trans. Electron Devices 51, 663, (2004).
[3] K. Suzuki, H. Tashiro, K. Narita, and Y. Kataoka, IEEE Trans. Electron Devices 35, 659, (1988).
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[7] K. Miyano, I. Mizushima, A. Hokazono, K. Ohuchi, Y, Tsunashima, IEDM Tech Digest, p. 433, (2000).
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[18] R. Lindsay, S. Severi, B. J. Pawlak, K. Henson, A. Lauwers, X. Pages, A. Satta, R. Surdeanu, H. Lendzian, and K. Maex, “SPER Junction Optimisation in 45nm CMOS Devices”, IEEE, 2004
Chapter 4
Physical Properties and Electrical Characteristics of Boron/Phosphorous Implanted Through Silicide
4.1 Compare conventional dopant activation and 2-step RTA result of IIS dopant activation
From the data of sheet resistance, we could obtain the result which about dopant activation ability of different situation. In the experimental samples, we used four-point probe to measure the sheet resistance is because that the accuracy of Spreading Resistance Profiling(SRP) in the shallow junction is not enough. So we used four-point probe structure to measure the sheet resistance of experimental and comparison samples and compared them. In order to measure the sheet resistance of shallow junction dopant activation, we must remove the silicide and the method is mentioned in chapter 3. The result of measurement was shown in Fig.4.1(a)(b) and we can obtain that when annealing temperature increased, the sheet resistance would decrease.
This method does measure the bulk junction activation so we would get the results of Fig.4.1. The following we compared were the different implanted dopant samples. Because the solubility of phosphorous and electron mobility was higher than boron, the measured sheet resistance of phosphorous
This method does measure the bulk junction activation so we would get the results of Fig.4.1. The following we compared were the different implanted dopant samples. Because the solubility of phosphorous and electron mobility was higher than boron, the measured sheet resistance of phosphorous