The table 4.3 lists the information of test bench which we use in multi-layer routing problem. The table 4.4 list the results of our algorithm and [2], and we compare the cost with [2]. The algorithm of CC means the simple algorithm, based on the construction by correction approach in [2]. It first constructs a minimum spanning tree for all pins, then transforms slants edges into vertical / horizontal edges to form an initial Steiner tree. Finally, it replaces the edges overlapping obstacles with edges around the obstacles with a smaller cost.
The table 4.4 list the cost and the number of via. The cost means wirelength +
Table 4.2: The comparison on the CPU time in single layer cases. Our run time is worse than other approaches in a lot of cases. The diminution of the performance comes from the difference of connection graph and topology construction.
Pin Obs. [20] [14] [19] Ours Rc1 10 32 <0.01 <0.01 <0.01 <0.01
Rc2 74 625 0.1 X 0.07 0.21
Rc3 115 1024 0.21 X 0.14 0.73
Rc4 10 10 <0.01 <0.01 0.02 0.01 Rc5 30 10 <0.01 <0.01 0.02 0.01 Rc6 50 10 <0.01 <0.01 0.06 0.02 Rc7 70 10 <0.01 <0.01 0.09 0.03 Rc8 100 10 <0.01 0.01 0.14 0.05
Rc9 100 500 0.31 0.24 0.81 1.29
Rc10 200 500 0.36 0.43 1.16 1.96 Rc11 200 800 1.53 0.83 2.02 3.74 Rc12 200 1000 1.8 0.91 2.72 4.87 Rc13 500 100 0.27 0.61 1.73 6.13 Rc14 1000 100 0.81 3.15 10.05 14.72
C * number of vias. We compared our cost with the algorithm in [2] and then shown in the cost reduction column. Here, we set C=3 to be the constant in these cases.
The table 4.5 list our cup time and we compared the cpu time with the algorithm in [2] and then shown in the run time reduction column. We can easily see the CPU time is faster than [2]. When the case size become larger, the saving of CPU time is fabulous. The algorithm in [2] is propagated the pins to other layers. The solution space at the algorithm is fabulous at large case, even they not propagate pins to every layer at big case.
In addition, the rc14 in single layer and the rt5 in multi-layer are both containing 1000 pins and 100 obstacle. However, we spend more CPU time in rc14 than in rt5.
The reason is all the pins and obstacles locate at the same layer in rc14, and the pins and obstacles locate at different layers in rt5. The cpu time of constructing connection graph depends on the number of pins and obstacles in one layer. Our algorithm will have higher performance in multi-layer.
Figure 4.1 and 4.2 are shown one of single layer rouging result and one of multi layers routing result projected to a plane without showing the obstacles.
Table 4.3: We list the information of test bench which we use in multi layer problem.
The information include the number of pins, obstacles and layers.
Pin Obs. Layer
ind1 50 6 5
ind2 200 85 6
ind3 250 13 10
ind4 500 100 5
ind5 1000 20 5
rt1 25 10 10
rt2 100 20 10
rt3 250 50 10
rt4 500 50 10
rt5 1000 100 5
Figure 4.1: The single layer routing result of Rc13. The number of pins is 500, and the number of obstacles is 100.
Table 4.4: The cost and the number of vias of the algorithm in [2] and ours in multi-layer cases. The cost is wirelength + C * number of vias and the cost reduction means the results of the algorithm in [2] compared with ours. We set C=3 to be the constant in these cases.
Ours CC[2] Cost ML-OASG[2] Cost
Cost Via Cost Via reduction Cost Via reduction
ind1 62809 33 82556 59 23.92% 56177 49 -11.81%
ind2 14296 150 17568 293 18.62% 12689 223 -12.66%
ind3 13218 252 17837 529 25.89% 11047 359 -19.65%
ind4 76738 0 273235 0 71.92% 77509 0 0.99%
ind5 14473173 0 23314944 0 37.92% 14656729 0 1.25%
rt1 4781 13 5095 91 6.16% 4379 76 -9.18%
rt2 11292 134 12885 290 12.36% 9623 215 -17.34%
rt3 18221 361 23233 705 21.57% 15801 490 -15.31%
rt4 25984 632 29464 1282 11.81% 22355 922 -16.23%
rt5 31310 719 38702 1102 19.1% 28213 863 -10.98%
Table 4.5: The list of the CPU time by the algorithm in [2]. We compared our run time with the ML-OASG algorithm in [2] and list in ”run time reduction” column.
[2] is performed on a 2.8 GHz AMD-64 machine with 8 GB memory and ours is performed on a 2.8 GHz AMD-64 machine with 2 GB memory
CC[2] ML-OASG[2] Ours Run time Run time Run time Run time reduction
ind1 0.02 0.06 0.01 91.67%
Figure 4.2: The routing result of rt4. All pins and path are projected to a plane, without showing the obstacles. The number of pins is 500, and the number of obstacles is 50.
Chapter 5
Conclusions and Future Works
In this thesis, we have proposed an algorithm, which can get good solution at single layer and fast yet effective at multi layers. The solution is limited by topology, but previous routing result at completed layers can provide an effective approach in multi layers. Experimental results have shown that our algorithm is still effective in larger case. The idea to estimate the co-edge is good for wirelength saving. It is better than just considering the U-Shaped refinement.[20]. Our algorithm and [20]
have the same topology, but our results are better than [20]. In multi-layer cases, we proposed a hierarchical and heuristic approach to solve this problem. Experimental results have shown that our algorithm is still efficient in larger multi-layer cases, with slightly more wirelength.
The results of our algorithm lost in some cases in single layer. The reason is the different of topology. In the multi-layer cases, the orders of layers handling will affect the results. If we improve the method to get efficient MST topology and the order of layers, we should get higher performance. The run time of our algorithm in single layer is a little large. There are two reasons for higher run time. One is the construct of the penalty MST and the other is the construction of Hanan points graph. We spent a lot of time at obstacle points construction in the construction of Hanan points graph step.The time on the construction is large, but the time on
the search is small. Because of the graph information we can decide the routing path easily in multi-layers. And then, we can add the buffer insertion step into the routing flow. The routing problem with timing driven might be the good target.
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作者簡歷
洪禎徽，民國七十年二月出生於台中市。民國九十三年六月畢業於國立中央 大學電機工程學系，並於九十四年九月進入國立交通大學電子研究所就讀，從事 VLSI 實體設計方面相關研究。民國九十六年十月取得碩士學位，碩士論文題目 為『使用規則導向且考慮障礙物之多層直角史坦納樹的建造』。