Chapter 1 Introduction
1.2 Organization
This thesis is composed of six chapters. We introduced research motivation for ADC BIST in this chapter. In chapter 2﹐ADC are classified into three categories. We discuss their structure﹐operational and characteristics. BIST circuits of ADC are also discussed briefly. In chapter 3﹐we design a pipeline ADC. That includes sample-and-hold circuits﹐3-bit flash ADC﹐3-bit DAC﹐residue amplifier and digital error correction circuits. In chapter 4﹐we bring up new idea of BIST of ADC. It uses probability to collect statistics to test the pipeline ADC.
In chapter 5﹐the circuits schemes of building block and their simulation results are presented.
In chapter 6﹐conclusion and future work are given.
Chapter 2 Brief introduction of ADC and BIST
2.1 ADC Review
Analog-to-digital converters transforms analog signals to digital ones. In the analog input dynamic range﹐ADC transform it related digital output code. It is shown in Fig. 2-1. As shows in Fig. 2-1(a), it is a simple diagram of ADC. As shows in Fig. 2-1(b), it is a simple transfer curve of an ADC.
Fig. 2-1, Simple ADC circuits Analog Input ADC
Digital Output
Analog Input Digital Output
bn-1 bn-2
b0
000 011 111
Fig. 2-1(a)
Fig. 2-1(b)
testing the DNL﹐INL﹐offset error and gain error﹐the basic functionality of ADC can be defines the value at code i in DNL and INL.
Fig. 2-2, Illustration of ADC parameter 11 Digital output
Analog output Ideal transfer curve
Actual transfer curve
+
(a) Ddifferential nonlinearity error (DNL) :
The DNL is the deviation of actual step width from the ideal value of 1 LSB. For example in Fig. 2-2﹐DNL(1)= -1LSB.
(b) Integral nonlinearity error (INL) :
The INL is the deviation of actual step transition point from the ideal step transition point. For example in Fig. 2-2﹐INL(2)= - .
(c) offset error (Vos) :
The offset error is the difference between the ideal and actual voltage at the lowest code as shown in Fig. 2-2.
(d) gain error (Ge) :
The gain error is the difference between the ideal and actual voltage at the highst code as shown in Fig. 2-2.
) 1 (
Vaw
) 2 (
Vat Vit(2)
2.2 Three Architectures of ADC
2.2.1 Flash Architecture
Flash ADC architecture is shown in Fig. 2-3. The flash architecture consists of comparators﹐a resistor string﹐and a decoder. The flash architecture does not need explicit front-end sample-and-hold (S/H) circuits. Only one clock cycle is needed to perform data conversion. The flash architecture is the simplest and fastest A/D converters. The number of comparators and reference voltages grow exponentially with the resolution. So the chip size and power consumption will become excessively large for the resolution above 6 bits.
Fig. 2-3, Flash ADC
Vref+ Vin
bn-1 bn-2
b1 Encoder
b0 Digital Output
Vref-1 2N −
2.2.2 Two-step Architecture
Because flash architecture use many comparators and resistor﹐two-step architecture improve its disadvantage. It can reduce comparators and resistor. The block diagram of a two-step architecture is shown in Fig. 2-4. It is include a coarse flash MSB ADC section ﹐a fine flash LSB ADC section﹐S/H circuits﹐digital -to- analog data converters (DAC) and residue amplifier. As the Fig. 2-4﹐it is N+M bits of two-step ADC. First﹐the N-bit MSB ADC determines the first N-bits. Secondly﹐we use DAC to transfer N-bits digital signals to an analog one. Then﹐input signals is subtracted off that value﹐called residue value. Finally﹐the residue value is amplified and the LSB are determined using the m-bit LSB ADC.
Fig. 2-4, Two-step ADC - +
S/H Coarse
N-bit ADC
Coarse N-bit ADC DAC
N bits M bits
N+M bits Summation Vin
2N
2.2.3 Pipeline Architecture
In the pipeline architecture﹐it is like two-step architecture. But the pipeline architecture needs more stages. Each stage has a S/H circuits﹐a low-resolution ADC﹐a DAC﹐a residue amplifier. Input signal is ampled S/H circuits. Then low-resolution ADC transform digital outputs of this stage. The output signals of DAC are subtracted out of the hold voltage in residue amplifier. The residue signals is transmitted to next stage where the process is repeated. The pipeline architecture is shown in Fig. 2-5. Add all digital output of each stage in digital error correction circuits to produce final outputs.
Fig 2-5, Pipeline ADC
Pipeline architecture has the advantage of flash ADC. It can reduce chip area and power construction. But﹐how many stages in the pipeline architecture and how many bits in each stage require careful design. For example of an 8-bit ADC﹐first situation is two stage (5-4 bits). Second situation is seven stages (2-2-2-2-2-2-2 bits). For first design﹐the residue amplifier must amplify 16 times. But residue amplifier must amplify 2 times of second design.
Because of settling time﹐The second design is faster than first situation. But the second Stage 3
Digital Correction
3 bits 3 bits 3 bits 2 bits
Digital output 8-bits
Stage 2
Stage 1 Stage 4
Vin
design must has higher resolution because of there are more bits in the next stage.
As shown in the Table 2-1﹐It is to compare the more stage and less stage which is better.
With more stages, it has high speed potential﹐high latency﹐small cap array and large operational amplifier size. With less stages, it has high resolution potential﹐low latency﹐high scale down ratio and large cap array.
Table 2-1, Number of stage of pipeline ADC
Number of stage Structure Gain per stage Number of comparator
7 2b*7 2 14
4 3b*3+2b 4 21
2 5b+4b 16 45
2.3 BIST Review
Built-in self-test circuits builds in the chip with device-under test. BIST circuits allows the DUT to evaluate its own quality without elaborate automatic test equipment. The DUT also can be tested in parallel by BIST circuits and automatic test equipment. BIST circuits requires a little more power consumption. There are some advantages and disadvantages in the Table 2-2.
Table 2-2, Advantage and disadvantage of BIST
Advantage
Build test circuits on chip
Reduce input/output pin signals traffic Permit testing easily
Reduce test cost Reduce test time At-speed testing
Disadvantage
Area overhead
Capability for system test
2.4 Two Works for BIST
2.4.1 Huertas’s Work
Fig. 2-6 shows the BIST scheme for structural testing of pipeline ADC. The strategies relies on reconfigured as A/D-D/A block, and tests each of ADC stages by applying a set of analog values. These values are DC stimuli giving a simple output signature. The technique is intended for being used in pipeline converters of arbitrary number of conversion stages and with a digital self-correction mechanism. It sends specific analog signals and digital count to each stage. Then, it compares the analog value and digital count with signals from the stages.
If they are all equal, anatest and digtest are set pass. If they are one or all are not equal, anatest and signals are set fail [1].
Fig. 2-6, Huertas’s work
2.4.2 Lee’s Work
Fig. 2-7 shows a BIST structure to test the static specification of ADC. A ramp signals generated by integrator serves as a test input signals. A specific range of this signals is divided into segments, with each segment corresponding to one output combination of n+1-bit counter, where n is the number of bits of ADC under test. The testing process is done with digital data processing by comparing the output of ADC under test with output of the n+1-bit counter [2].
Fig. 2-7, Lee’s work 2N+1
Chapter 3 50 MHz / 8-bits Pipeline ADC
3.1 Abstract
In the chapter﹐we propose to design a 8-bit, 50 MHz pipeline ADC. We select four stages (3-3-3-2 bits structure)﹐as shown in Fig. 3-1. Each stage has a S/H circuits﹐a low-resolution ADC﹐a DAC and a residue amplifier. With digital error correction circuits﹐it can reduce offset error and increase resolution. Clock generator generates different clock signals for the internal circuits. The S/H circuits uses double-sampling architecture. It can sample two times in an unit time than traditional S/H circuits.
Vin
Stage 3 Digital Correction
3 bits 3 bits 3 bits 2 bits
Digital output 8-bit
Stage 2
Stage 1 Stage 4
S/H
ADC
X 4 +
-DAC Stage 2
3.2 ADC Architecture Overview
All circuits of pipeline ADC which we design are shown as the flow.
a. 50MS/s S/H circuits:
z Folded-cascode Op.
z Double Sample S/H circuits.
b. 3-bits A/D converters:
z Pre Amplifier.
z Comparator.
z Encoder.
z Bubble correction.
c. 3-bits D/A converters:
z Resistor D/A converters.
d. Residue amplifier:
z Residue amplifier.
e. Digital Error Correction:
z Digital Error Correction.
z D flip-flop.
f. Clock Generator:
z Clock Generator.
3.3 Sample-and-Hold circuits
3.3.1 Double-sampling S/H
In the analog-to-digital converters﹐the sample-and-hold circuits is very important. It is a key module in designing an ADC. The double-sampling architecture is shown in Fig. 3-2.
Switches of transistor M5/M6/M7/M8/M13/M14/M15/M16 control the capacitor to sample or hold signals. Our goal is 50 Mega Sample per second with a resolution of 8 bits and error is less than 1.5625mV (1/2 LSB). It’s dynamic range is 0.8 V (peak-to-peak).
＋
－
In+
In-Out+
Out-cmi
cmi cmi cmi
dc1
dc1 dc1
c1
dc1
dc1 dc2 dc2
dc2 dc2 dc2
dc2 dc1
c1
c2 c2
C1
C2
C3
C4
The double-sampling S/H﹐uses two pairs capacitors to sample and hold in turns. When one pair is sampling input signals﹐another hold previous input signals. As shown in Fig. 3-3﹐
C1/C4 sample input signals and C2/C3 and OPA become close-loop to hold previous input signals. In the next clock phase﹐the two pairs capacitors exchange their work.
C1/C4 holds signals and C2/C3 sample signals. It has two times of sample output in unit time.
Fig. 3-3, Operational of double-sampling architecture
Because of double-sampling, it has two outputs in one clock. But traditional S/H only has one outputs in one clock. That is shown in Fig. 3-4.
Fig. 3-4, Compare traditional S/H and double sampling S/H S
S
S
H H
H H
H H
H Input signals
Output signals
Traditional S/H Double-sampling S/H
S : sample mode H : hold mode
3.3.2 Operational Amplifier
In the sample-and-hold circuits﹐the operational amplifier is very important. It is the key point to design S/H circuits. The unit-gain frequency and slew-rate decides the speed of the S/H circuits. The gain decides the gain error of the S/H circuits. Output swing decides the dynamic range of the S/H circuits.
a. 8-bits resolution﹐0.8 mV dynamic range (peak-to-peak).
b. 8-bits resolution﹐settling time is less than 10ns (half of 20ns).
We use folded-cascode operational amplifiers﹐shown in Fig. 3-5. Its advantage is large output swing. Output and input can have the same common-mode level.
Vb4
In the fully-differential operational amplifier﹐we need common-mode feedback (CMFB) circuits to hold on the voltage of common-mode output. It lets the output swing of operational amplifier to have the same datum point. We use dynamic CMFB circuits. In coordination to the double-sampling architecture﹐two pairs capacitor work to take turns. It is shown in Fig.
3-6.
Fig. 3-6, Common-mode feedback circuits
There are two pairs of CMFB circuits﹐left side is the one and right side is another.
They are feedback in turns. So﹐we only analysis the right hand side﹐M3/M4. When dclk2 is high﹐MC6/MC7/MC11 are open﹐CM3/CM4 charge the difference of CMO and Bias. When dclk1 is high﹐MC5/MC8/MC12 are open﹐the charge of CM3/CM4 share the charge with and Cmb. If the common-mode voltage of have offset﹐the voltage difference will be feedback to the operational amplifier to calibrate level.
cmo
dc2 cm1
dc2 dc2 dc2 dc2
dc2
dc1 dc1 dc1 dc1
dc1 dc1
cm2 cm3 cm4
Out+ Out- Out+
Out-cmb
bias
− + Out
Out / Out+ Out/ −
− + Out Out /
As shown in Fig. 3-7, it is the simulation results of folded-cascode operational amplifier.
We calculate that the gain of operational amplifier must be 56dB and unit-gain frequency must higher than 310 MHz. The parameters are shown in Table 3-1.
Fig. 3-7, Simulation of folded-cascode operational amplifier
Table 3-1, Parameters of folded-cascode operational amplifier DC Gain Unit-Gain
frequency
Phase Margin
I/P CM O/P CM Dynamic
Range 56 dB 570 MHz 60 deg 0.9 v 0.9 v 0.8 v
3.4 3-bit Flash ADC
In the flash 3-bit ADC﹐it includes Pre-Amplifier﹐Comparator﹐Encoder and Bubble correction circuits. It is shown in Fig. 3-8. First, input signal ( ) compares with eight reference voltages levels respectively. And then, the comparison results are corrected by bubble correction circuits. The correction circuits can reduce effect of meta-stability. Finally, the improved thermometer will be transferred to binary code by encoder.
Fig. 3-8, 3-bit flash ADC Pre-amplifier + comparator
Vref+ Vin
b7 b6
b2 b1 Bubble
Correction
b4 b3 b5 Encoder
b0 Digital Output
Vref-Vin
3.4.1 Pre-Amplifier
The voltage offset error of comparator will cause error during comparing process. It is an important factor to affect the resolution of ADC. So﹐the pre-amplifier can amplify the input signals to reduce the affect of offset error for comparator. As shown in Fig. 3-9﹐it is differential difference component. The first stage amplifies the difference between input signals and reference signals. Then the difference will be transfer to the second stage. We hope the gain of pre-amplifier is bigger then eight times. Then﹐we look the offset voltage is become 1/8 of the original in the comparator. For example﹐if the voltage offset error is 24 mV in the comparator﹐it is 3 mV in pre-amplifier forward. If the difference between input signals and reference signals are too small, it will affect the meta-stability. The pre-amplifier can reduce the affect of meta-stability.
Fig. 3-9, Pre-amplifier circuits
In- In+Re- Re+
Vb
Out+ Out-
3.4.2 Comparator
As shown in Fig. 3-10﹐it is a latch type comparator. When the clock is low﹐it is in the reset mode. and reset to vdd. When the clock is high﹐it is in the latch mode.
A comparator compares the difference between and signals. When one of sets to high level, the other will set to low level.
Fig. 3-10, Comparator
cn cn
cn
In Ref
Out+
Out-Cn
Cn
In Ref +
Out Out−
−
+ Out
Out and
3.4.3 Bubble correction
Because of meta-stability﹐there is an error code in a group codes. For example﹐it is shown in Fig. 3-11. Left side is correct input. Input is 0-0-1-1-1 and output is 0-0-1-0-0-0. In right side﹐input is not correct 0-0-1-0-1. But we use the bubble-correction to calibrate it.
Therefore the output is also correct.
Fig. 3-11, Bubble correction circuits 0
0
1
1 1 1 1 0 0
0 0
0 0 0
0 0
1 1 0 1 0 0
3.4.4 Encoder
We want to transfer the thermometer to output code of 3-bit. It is shown in the Table 3-2.
Table 3-2, Encode to 3-bit output a6 a5 a4 a3 a2 a1 a0 d2 d1 d0
1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
Encoder architecture is shown in the Fig. 3-12. We use three 3-input OR-gate to encode the input code.
Fig. 3-12, Encoder d2=a6+a5+a4
d1=a6+a3+a2 d0=a5+a3+a1
Encoder [a6:a0]
d2 d1 d0
3.5 3-bit DAC
Digital-to-analog converters uses serial resistors to divid the reference voltage into several voltage value. Da+ and Da- select output of +3/4Vref﹐+1/2 Vref﹐+1/4 Vref, -3/4 Vref, -1/2 Vref﹐-1/4 Vref and 0. We must decide the size of switch carefully. It considers turn-on resistor of switch. Da+ and Da- signals must to be steady-state as fast aswell. It is shown in Fig. 3-13.
Fig. 3-13, Series resistor DAC
Vref+ Vref- Da+
Da-a6a0 a6a0 a1
a1 a5
a5 a2
a2 a4 a4 a3
3.6 Residue Amplifier
As shown in Fig. 3-14﹐it is residue amplifier circuits. It must operate in overall range. It must auto zero to reduce the offset error of operational amplifier.
Fig. 3-14, Residue amplifier
In order tohold the charge of capacitors﹐dc1 and dc2 is non-overlapping. We use a skip named bottom-plate sampling. Before dc1 set to low﹐c1 has already turned to low. It lets charge injection and input signals are not correspond. There is no offset error from operational amplifier. Because the offset error is cancel by the virtual short. The clocks are shown in Fig.
3-15.
Fig. 3-15, Non-overlapping clock
＋
－
cmo
Out+
Out-dc1
Ca1
cmi Cs1
cmo Ca2
Cs2 In+
In- Da+
Da-
dc1
dc1
dc1 dc1
dc1 dc2
dc2
dc2
dc2 c1
c1
c1
c1 dc1 dc2
First﹐when dc1/c1 is high﹐it is shown in Fig. 3-16. Cs1/Cs2 charges the input signals.
Input and output of operational amplifier connect the common-mode voltage of in and out.
Second﹐when dc2 is high﹐it is shown in Fig. 3-17. Cs1/Cs2 connects Da+/Da- to charge. The difference charge of In and Da transfer to Ca1/Ca2. When Cs=4Ca﹐then Out=4*(In-Da).
Fig. 3-16, Sample mode of residue amplifier
＋
－
cmo
Out+
Out-cmi
Ca1
cmi Cs1
cmo Ca2
Cs2 In+
In-
c1
c1
＋
－
Out+
Out-Ca1
Cs1
Ca2 Cs2
Da+
Da-
3.7 Digital Error Correction
Digital error correction circuits can reduce offset error and increase resolution. The principle is the MSB of next stage to calibrate the LSB of this stage. The final output value is the sum of each stage’s output﹐it is shown in Fig 3-18.
LSBLSB MSBMSBMSB LSBLSB MSB
LSB LSB MSB
MSB LSBLSB MSB
MSB
LSB LSB MSB
MSB LSBLSB MSB
MSB
LSBLSB MSBMSBMSB LSBLSB MSB
Out7 Out6 Out5 Out4 Out3 Out2 Out1 Out0
Fig. 3-18, Final output of digital error correction
There are two steps. First﹐Keep the compare level to shift right 1/2LSB. Second﹐reduce the gain of amplifier two times. Originally we amplify the gain is 8. But now﹐we amplify only 4. Fig. 3-19 is traditional transfer curve of 3-bit ADC. Fig. 3-20 is shift transfer curve of 3-bit ADC.
Fig. 3-19, Traditional transfer curve Residue
Vin
000 001 010 011 100 101 110 111
Vref+
Vref- 0
Fig. 3-20, Shift transfer curve Residue
Vin
000 001 010 011 100 101 110
Vref+
Vref- 0
½ Vref+
½ Vref-
3.8 Clock Generator
Clock generator is shown in Fig. 3-21. In the switch capacitor circuits﹐all switchs are controlled by internal clock which is generated by clock generator. It has two modes. One is sample mode and the other is hold mode. The clocks must be non-overlapping in order to guarantee charge is not inadvertently lost. It is shown in Fig. 3-22. Dc1 and dc2 are non-overlapping.
Fig. 3-21, Clock generator
Fig. 3-22, Clocks of clock generator NOR
NOR
delay
delay clk
c1d
c2d delay
delay
c1
c2
c1 dc1 c2 dc2
Non-overlapping
Chapter 4 Built-In Self-Test of ADC
4.1 Overview
In the chapter﹐we propose a new approach to test pipeline ADC. It gathers statistic about probability to test pipeline ADC. We test the offset error and gain error by the output signals of the S/H in each stage. Then﹐we design the BIST circuits. We realize the BIST circuits and pipeline ADC on the same chip.
4.2 Ideal Analysis for ADC
We design the four stages pipeline ADC. Output code of first, second and third stage is 3-bit. Output code of fourth stage is 2-bit. They are shown in Fig.4-1.
S/H
ADC DAC
X 4 +
-S/H
ADC
X 4 +
-S/H
ADC DAC
X 4 +
-S/H
DAC ADC Input
Stage 1 Stage 2 Stage 3 Stage 4
s1 s2 s3 s4
s1 s2 s3
da3 da2
da1
If pipeline ADC is ideal﹐the equation of s1, s2, s3 and s4 is as the follow:
The overall range of input signals is +400 mV ~ -400 mV. We divide the overall range into three parts. Part-A (Pa) is -400 mV ~ -150 mV. Part-B (Pb) is -150 mV ~ +150 mV.
Part-C (Pc) is +150 mV ~ +400 mV. It is shown in Fig. 4-2.
Fig. 4-2, Distribution of Pa and Pb and PC.
If we send ramp signals to the input of the pipeline ADC﹐we can get the four signals.
-150
The signals s1 is the stage 1 output of the S/H, as shown in Fig. 4-3. The signals s2 is the stage 2 output of the S/H, as shown in Fig. 4-4. The signals s3 is the stage 3 output of the S/H, as shown in Fig. 4-5. The signals s4 is the stage 4 output of the S/H, as shown in Fig. 4-6. All of s1, s2, s3 and s4 are triangle signals. The frequency of the following stage is higher than the pervious stage. Frequency of s2 is four times s1. Frequency of s3 is four times s2﹐and so on. The overall range is +400 mV ~ -400 mV. We divide the full range into three parts. Part-A is -400 mV ~ -150 mV. Part-B is -150 mV ~ +150 mV. Part-C is +150 mV ~ +400 mV. We can calculate probability of Part-A, Part-B and Part-C in each stage. Stage 1 is Pa1 and Pb1 and Pc1 shown in equation (6), (7) and (8). Stage 2 is Pa2 and Pb2 and Pc2 shown in equation (9), (10) and (11). Stage 3 is Pa3and Pb3 and Pc3 shown in equation (12), (13) and (14). Stage 4 is Pa4 and Pb4 and Pc4 shown in equation (15), (16) and (17).
4.2.1 Ideal Probability of Stage 1
Fig. 4-3, Ideal signals of S/H for stage 1.
(7) . 3125 . 250 0 1 1
(6) . 800
=
=
=
= Pa all Pc all
4.2.2 Ideal Probability of Stage 2
Fig. 4-4, Ideal signals of S/H for stage 2.
Fig. 4-4, Ideal signals of S/H for stage 2.