In this section, we will show our research efforts. This thesis is organized as follow:
In chapter 1, the overview of Poly-Si TFTs, the brief introduction of silicided process, and motivation in this thesis are described.
In chapter 2, experimental process flows, and electrical parameter extraction are shown.
In chapter 3, for n-channel Poly-Si TFTs, we will show Ni salicided process can decrease parasitic resistance, passivate defects, and suppress floating body effect to obtain the better performances of device. Moreover, the performances of FSA-TFTs with in-situ doped gate and FSA-TFTs with un-doped gate are compared with the conventional TFTs. In addition, we discuss the influence of the different RTA temperature and time, and difference between fully and partially Ni-salicided S/D and gate at the same time. For p-channel Poly-Si TFTs, we will show Ni salicide process can decrease parasitic resistance evidently and passivate defects to obtain the better performance of device as well. The performances of FSA-TFTs with un-doped gate are compared with the conventional TFTs.
In chapter 4, at the end of this thesis, we will make conclusions and future works.
Chapter 2
Experimental Process and Electrical Parameters Extraction
2.1 Fabrication of Poly-Si Thin-Film Transistors (Poly-Si TFTs)
In this section, the process flows of poly-Si thin-film transistors are described, including the process flows of the fully Ni self-aligned silicided TFTs (FSA-TFTs) and the conventional TFTs.
2.1.1 Fabrication of the FSA-TFTs
The process flows of devices are showed in Fig.2-1. First, a 550-nm thick oxide was deposited on the 6-in wafers. Then, a 50-nm thick amorphous-Si (a-Si) layer was deposited as the active layer in a LPCVD system using SiH4 as source at 550°C. Next, the a-Si was crystallized to poly-Si by solid phase crystallization (SPC) process at 600°C for 24 hours.
After the wafers were subjected to photolithography for active region definition, a 50-nm thick tetraethoxysilane (TEOS) gate dielectric layer, a 50-nm a-Si layer were deposited, and nitride was deposited by LPCVD as hard mask. The a-Si gate layers were divided into in-situ n+ phosphorus doped gate or un-doped gate. After patterning of the gate electrode, the nitride layer and the a-Si layer were etched by the oxide dry etcher (TEL-5000) and poly-Si dry etcher (TCP-9400), respectively. Then the gate oxide was removed by HF-dip. Subsequently, a self-aligned ion implantation was used to form n+ S/D with phosphorous (p+) at 20 keV to a does of 5×1015 cm-2, and p+ S/D with BF2+ at 25 KeV to a dose 5×1015 cm-2. Dopants were activated in a furnace at 600oC for 12 hours. Next, the TEOS oxide was deposited and etched to form the sidewall spacer. Then, the Si3N4 hard-mask layer was selectively etched by a hot phosphoric acid (H3PO4). After a HF-dip for 10-sec, a 40-nm thick Ni and a 10-nm thick TiN were deposited on the wafer by Metal-PVD, and then the fully Ni-salicided S/D and gate was carried out at 500°C for 30 seconds or 500°C for 60 seconds by one-step rapid thermal
annealing (RTA) in the N2 ambient. Finally, the unreacted TiN and Ni were selectively removed by sulfuric acid (H2SO4). Before measurement, an NH3 plasma treatment was performed to passivate the crystalline defects.
2.1.2 Fabrication of Conventional TFTs
In addition to the fabrication of FSA-TFTs, conventional TFTs were fabricated as the control ones. The structure of conventional TFT is showed in Fig.2-2. First, a 550-nm thick oxide was deposited on the 6-in wafers. Then, a 50-nm thick a-Si layer was deposited as active layer in a LPCVD system. Next, the a-Si was crystallized to poly-Si by SPC process at 600°C for 24 hours. Then, the wafers were subjected to photolithography for active region definition. After a 50-nm thick TEOS oxide layer, one of the two wafers was deposited a 200-nm in-situ doped a-Si layer in a vertical furnace as n+ gate, the other was deposited a 200-nm a-Si layer in LPCVD system and then it was ion implanted by Boron (B+) at 25 keV to a dose 5×1015 cm-2 as p+ gate. Next, after gate patterning, gate dielectric layer on S/D region was removed by HF-dip. Subsequently, a self-aligned ion implantation was used to form n+ S/D with phosphorous (p+) at 20 keV to a does of 5×1015 cm-2, and p+ S/D with BF2+
at 25 keV to a dose 5×1015 cm-2. Dopants were activated in a furnace at 600°C for 12 hours.
Then, 300-nm passivation oxide was deposited by PECVD and patterned for contact holes opening. Finally, a 500-nm thick Al was immediately thermal evaporated, followed by lithography for Al pad pattern definition. Before measurement, an NH3 plasma treatment was performed to passivate the crystalline defects.
2.2 Electrical Parameters Extraction
In this section, all the electrical characteristics of proposed poly-Si TFTs were measured by HP 4156B-Precision Semiconductor Parameter Analyzer. Moreover, the methods of parameter extraction used in this study are described. These parameters include threshold voltage (VTH), field-effect mobility (μFE), subthreshold swing (S.S.), parasitic resistance (RP),
ON current (ION), OFF current (IOFF ), ON/OFF current ratio (ION/IOFF).
2.2.1 Threshold Voltage (V
TH)
The threshold voltage VTH is an important parameter required for the channel length-width and series resistance measurements. However, VTH is not unique defined.
Various definitions exist and the reason for this can be found in the ID-VG curves. One of the most common threshold voltage measurement technique is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of 50~100 mV typically to ensure operation in the linear MOSFET region [41].
However, in this thesis, the threshold voltage is defined at a low drain voltage of 0.5V, and a fixed drain current ID=IDN×(W/L) where IDN is a normalized drain current. Here, IDN is 100 nA for n-channel and 10nA for p-channel.
2.2.2 Field Effect Mobility (μ
FE)
Usually, field effect mobility (μFE) is determined from the maximum value of transconductance (gm) at low drain bias. The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, so that the first order of I-V relation in the bulk Si MOSFETs can be applied to poly-Si TFTs. The drain current in linear region (VDS＜VGS -VTH) can be approximated as the following equation:
2 ]
where W is the channel width, L is the channel length, VTH is the threshold voltage, Cox is the gate oxide capacitance per unit area. Thus, gm is given by
DS
Therefore, the field-effect mobility is
(max)
2.2.3 Subthreshold Swing (S.S.)
The drain current in the saturation region (VDS>VGS-VTH) is expressed as the following
equation:
It appears that the current abruptly vanishes while VG is reduced to zero from the equation. In reality, there is still some drain conduction current below threshold, and this is known as the subthreshold conduction. This current is due to the weak inversion in the channel between flat-band and threshold, which leads to a diffusion current from source to drain. The subthreshold swing (S.S.) is defined as the reciprocal of slope of the ID-VG curve in weak inversion region. It is the amount of gate voltage required to increase/ decrease drain current by one order of magnitude. It is a typical parameter to describe the control ability of gate toward channel. [38]
In this thesis, the subthreshold swing is defined as one-third of the gate voltage required decreasing the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
2.2.4 Parasitic Resistance (R
P)
The device parasitic resistances are extracted from their output characteristics. It is known that when devices are operated under low drain voltage and high gate voltage their measured resistance (Rm) can be expressed as
P
where Rch and Rp represent channel resistance and parasitic resistance. COX is the gate dielectric capacitance per unit area, and W, L, VTH are device channel width, length and threshold voltage, respectively. The parasitic resistance Rp can be extracted by plotting Rm
versus L for varying gate voltages. [42]
2.2.5 ON/OFF Current Ratio
A poly-Si TFT with good characteristics should have not only high ON state driving current but also low OFF state leakage current. For pixel transistors, the OFF state is
frequently encountered in normal operation. Therefore, ON/OFF current ratio is obviously a better evaluation parameter compared with ON state current alone. The leakage current mechanism in poly-Si TFTs is not like that in MOSFETs. In MOSFETs, the channel is composed of single crystalline Si and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly crystalline Si. A large amount of trap densities in grain structure attribute a lot of defect states in energy band gap to enhance the tunneling effect.
Therefore, the leakage current due to the tunneling effect is much larger in poly-Si TFTs than that in MOSFETs. Considering large negative gate bias VG is applied, a hole-channel forms under the gate. In principle, little current flows because the junction between the hole-channel and the drain is reverse-biased. However, due to the existing numerous trap states in the polysilicon film and the large electric field, electron and hole emission from trap states becomes a strongly increasing function of electric field. Here, a trap could be modeled by a potential well. For large electric fields, it is possible for electrons to escape the potential well by quantum mechanical tunneling. The tunneling rate increases strongly with electric field because the barrier thickness decreases. The effect is a rapid increase in leakage current. The tunneling rate depends upon the total electric field, and consequently the leakage current is highest when both drain and gate voltages are large. [38]
In this thesis, the ON current is defined as the drain voltage is 3V, and the drain current when gate voltage equals to 10 V for n-channel and gate voltage equals to 15 V for p-channel.
The OFF current is specified as the minimum current when drain voltage equals to 3 V.
3V
(1) 550-nm thick buried oxide and 50-nm thick a-Si were deposited.
(2) 600oC annealing for 24-hr and active region definition.
(3) 50-nm thick TEOS oxide, 50-nm thick a-Si and 100-nm thick nitride layer.
(4) Gate definition.
Buried oxide
a-Si
Buried oxide
Poly-Si
Buried oxide
Poly-Si TEOS
a-Si
Nitride
Buried oxide
Poly-Si TEOS Poly-Si
Nitride
(5) phosphorous implantation for n-channel and BF2+ implantation for p-channel.
(6) TEOS spacer formation.
(7) Nitride layer was etched by H3PO4.
Buried oxide
Poly-Si TEOS Poly-Si
Nitride S/D Implant
Buried oxide
Poly-Si TEOS Poly-Si
Nitride
Buried oxide
Poly-Si TEOS Poly-Si
(8) Ni and TiN deposition.
(9) Ni-salicide formation by RTA 500oC.
Fig.2-1 Process flows of fully Ni-salicided TFTs.
Buried oxide
Poly-Si TEOS TEOS Poly-Si
Buried oxide
Poly-Si
TiN Ni
Fig.2-2 The Structure of Conventional TFT.
Buried oxide
Poly-Si TEOS
Poly-Si
Chapter 3
Electrical Characteristics and Discussion of the n-Channel and the p-Channel FSA-TFTs
In this chapter, we will show electrical characteristics as well as discuss physical meaning for n-channel and p-channel. At first, the TEM photograph for cross-section of FSA-TFTs is shown in Fig.3-1 and the TEM photograph for cross-section of Source/Drain (S/D) junction is shown in Fig.3-2. Subsequently, basic characteristics of n-channel and p-channel are shown in session 3.1 and 3.3, respectively. Moreover, differences between fully-salicided and partially salicided n-channel TFTs with in-situ poly-Si gate are shown in session 3.2. Device parameters including threshold voltage (VTH), field-effect mobility (μFE), subthreshold swing (S.S.), parasitic resistance (RP), and ON/OFF current ratio are all extracted. These methods of extraction have been explained in session 2.2. Finally, we found that poly-Si TFTs with fully Ni-salicided S/D and gate structure for n-channel and p-channel have better electrical characteristics such as higher ON current, lower leakage current, stable VTH, higher field-effect mobility, alleviated VTH roll-off, improved subthreshold swing, increased breakdown voltage, and increased ON/OFF current ratio, etc.
3.1 Basic Characteristics of n-Channel FAS-TFTs with Undoped and In-situ Poly- Si Gate
In this section, we will explain the basic characteristics of n-channel FSA-TFTs. At first, the transfer characteristics of FSA-TFTs with undoped gate, in-situ gate, and conventional TFTs are compared in session 3.1.1. In addition, the output characteristics of FSA-TFTs with undoped gate, in-situ gate, and conventional TFTs are compared in 3.1.2. The floating-body effect of FSA-TFTs with undoped gate, in-situ gate, and conventional TFTs are compared in
3.1.3. The influence of metal RTA temperature and time for FSA-TFTs with undoped and in-situ poly-Si gate are compared in 3.1.4. The parasitic resistance of FSA-TFTs with undoped gate, in-situ gate, and conventional TFTs are compared in 3.1.5. Finally, the ON/OFF current ratio of FSA-TFTs with undoped gate, in-situ gate, and conventional TFTs are compared in 3.1.6.
3.1.1 Transfer Characteristics
Fig.3-3 and Fig.3-4 show the ID-VG transfer characteristics of conventional TFTs with W/L=10μm/10μm and W/L=10μm/0.8μm, respectively. Moreover, these figures show two different treatment steps for n-channel. Obviously, conventional TFTs with NH3 plasma treatment have better subthreshold swing, and higher ON/OFF current ratio. In addition, they have more stable VTH than conventional TFTs without NH3 plasma treatment.
Fig.3-5 and Fig.3-6 show the ID-VG transfer characteristics of FSA-TFTs with undoped gate, and W/L=10μm/10μm with different metal RTA at 500oC for 30 seconds and 60 seconds, respectively. Fig.3-7 and Fig.3-8 show the ID-VG transfer characteristics of FSA-TFTs with undoped gate, and W/L=10μm/0.8μm with different metal RTA at 500oC for 30 seconds and 60 seconds, respectively. In addition, Fig.3-9 and Fig.3-10 show the ID-VG transfer characteristics of FSA-TFTs with in-situ gate, and W/L=10μm/10μm with different metal RTA at RTA 500oC for 30 seconds and 60 seconds, respectively. Fig.3-11 and Fig.3-12 show the ID-VG transfer characteristics of FSA-TFTs with in-situ gate, and W/L=10μm/0.8μm with different metal RTA at RTA 500oC for 30 seconds and 60 seconds, respectively. From Fig.5 to Fig.12, all of FSA-TFTs have the same channel thickness 50nm and TOX=50nm. The drain voltage bias is 0.5V and 3.0V. It is noted that poly-Si TFTs with fully Ni-salicided process and NH3 plasma treatment have better subthreshold swing, higher ON/OFF current ratio, and more stable VTH than poly-Si TFTs without fully Ni-salicided process and NH3 plasma treatment, and poly-Si TFTs only with fully Ni-salicided process. The reasons for these
improvements may be due to two aspects, one is that fully Ni-salicided S/D is able to passivate the defects of S/D junction, and the other is that fully Ni-salicided gate is able to obtain the better value of COX. The NH3 plasma treatment can also passivate the defects of S/D surface and dielectric interface [43]. It is found that FSA-TFTs with RTA 500oC for 60 seconds have better S.S. and lower leakage current than FSA-TFTs with RTA 500oC for 30 seconds. So, RTA 500oC for 60 seconds is selected as the condition for comparison. The extracted values of VTH, S.S., and ON/OFF current ratio are shown in Table 3-1.
Fig.3-13 and Fig.3-14 show ID-VG transfer characteristics of n-channel FSA-TFTs with undoped gate compared with conventional TFTs. Ni-salicide is formed by RTA at 500oC for 60 seconds. Devices with W/L=10μm/10μm and W/L=10μm/0.8μm have been measured. The drain voltage bias is 0.5V and 3.0V. It is found that FSA-TFTs with NH3 plasma treatment have stable VTH, better S.S., and higher ON/OFF current ratio than without ones; it is also found that devices with fully Ni-salicided S/D exhibit a lower leakage current about 10-13
~10-14 order than conventional TFTs only with NH3 plasma. This may be due to the passivation of the defects of S/D junction during the silicidation process.
Fig.3-15 and Fig.3-16 show field-effect mobility of n-channel FSA-TFTs with undoped gate compared with conventional TFTs. The Ni-salicide is formed by RTA at 500oC for 60 seconds. Devices with W/L=10μm/10μm and W/L=10μm/0.8μm have been measured. The drain voltage bias is 0.5V. The values of field-effect mobility are deduced and shown in Table 3-2. It is found that both long-channel and short-channel FSA-TFTs have higher mobility than conventional TFTs. These improvements are due to that NSA-TFTs have better value of COX
for long-channel and reduced parasitic resistance for short-channel.
Fig.3-17 and Fig.3-18 show comparison of field-effect mobility between devices with W/L=10μm/10μm and W/L=10μm/0.8μm. Devices are n-channel FSA-TFTs with undoped gate and conventional TFTs, respectively. The Ni-salicide was formed at RTA 500oC for 60 seconds. It is found that FSA-TFTs with W/L=10μm/10μm and W/L=10μm/0.8μm exhibit the
same order of magnitude of mobility; however, conventional TFTs show a significant difference. This difference is due to the reduced parasitic resistance in FSA-TFTs, which shows no significant difference between long and short channel.
Fig.3-19 and Fig.3-20 show ID-VG transfer characteristics of n-channel FSA-TFTs with in-situ gate compared with conventional TFTs. The Ni-salicide was formed by RTA at 500oC for 60 seconds. Devices with W/L=10μm/10μm and W/L=10μm/0.8μm have been measured.
The drain voltage bias is 0.5V and 3.0V. It is found that FSA-TFTs with in-situ gate have stable VTH, better S.S., larger ON/OFF current ratio than conventional TFTs. The reason of these results is the same as FSA-TFTs with undoped gate.
Fig.3-21 and Fig.3-22 show field-effect mobility of n-channel FSA-TFTs with in-situ gate compared with conventional TFTs. The Ni-salicide was formed by RTA at 500oC for 60 seconds. Devices with W/L=10μm/10μm and W/L=10μm/0.8μm have been measured.
Fig.3-23 and Fig.3-24 show comparison of field-effect mobility between W/L=10μm/10μm and W/L=10μm/0.8μm for n-channel FSA-TFTs with in-situ gate and conventional TFTs, respectively. The drain voltage bias is 0.5V. The values of field-effect mobility are extracted and shown in Table 3-2. It is found that FSA-TFTs with in-situ gate have the same trends as FSA-TFTs with undoped gate.
3.1.2 Output Characteristics
Fig.3-25 shows comparison of ID-VD output characteristics between n-channel FSA-TFTs with in-situ doped gate, undoped gate, and conventional TFTs. The Ni-salicide was formed by RTA at 500oC for 60 seconds. Device with W/L=10μm/0.8μm has been measured at VG-VTH=0.5V, 1.0V, 1.5V, 2.0V, 2.5V. It is found that FSA-TFTs have a reduced kink effect and also an increased drain breakdown voltage. These results can strongly support that floating-body and parasitic BJT effects are significantly suppressed by the fully silicided S/D structure [44].
3.1.3 Floating-Body Effects
Fig.3-26 and Fig.3-27 show the comparison of floating-body effect between n-channel FSA-TFTs with undoped gate and in-situ gate and conventional TFTs. The Ni-salicide was formed by RTA at 500oC for 60 seconds. Device with W/L=10μm/0.8μm has been measured at VD=0.5V, 1.0V, 3.0V, 5.0V, 7.0V. From these figure, it is found that FSA-TFTs have suppressed floating-body effect compared with conventional TFTs.
Fig.3-28 shows comparison of threshold voltage roll-off between n-channel FSA-TFTs with in-situ doped gate, undoped gate, and conventional TFTs. Devices with W/L=10μm/0.8μm have been measured at VD=0.5V, 1.0V, 3.0V, 5.0V, 7.0V. The values of VTH are shown in Table 3-3. Fig.3-29 shows comparison of threshold voltage shift between n-channel FSA-TFTs with in-situ doped gate, undoped gate, and conventional TFTs. The dimension of device is W/L=10μm/0.8μm, and reference values of VTH are defined at VD=0.5V.
The reduced VTH roll-off and VTH shift strongly support that the BJT effect is significantly suppressed in the fully salicided S/D structure. Similar suppression of the floating-body effect is reported in deep silicidation of partially depleted SOI devices, where the thick silicide layer worked as a sink for holes [45]. The diagram of Floating-body effect is shown in Fig.3-66.
3.1.4 Influence of Metal RTA Temperature and Time
Fig.3-30 shows comparison of threshold voltage roll-off for n-channel FSA-TFTs with undoped gate at RTA 500oC for 30 seconds and 60 seconds. The channel width is 10μm, and the drain voltage bias is 0.5V. The values of VTH roll-off are shown in Table 3-4. We can find that FSA-TFTs with RTA 500oC for 60 seconds have less VTH roll-off than FSA-TFTs with
Fig.3-30 shows comparison of threshold voltage roll-off for n-channel FSA-TFTs with undoped gate at RTA 500oC for 30 seconds and 60 seconds. The channel width is 10μm, and the drain voltage bias is 0.5V. The values of VTH roll-off are shown in Table 3-4. We can find that FSA-TFTs with RTA 500oC for 60 seconds have less VTH roll-off than FSA-TFTs with