Organization

In Chapter 2, an overview of the method of logical effort is introduced. In the beginning of this chapter, the traditional circuit delay models are presented and the concepts of these models are interpreted, too. After that, the theory and the derivation of logical effort are defined and clarified. In the end of this chapter, several design examples with the method of logical effort are demonstrated and the related researches of logical effort are discussed.

In Chapter 3, the effects of temperature and supply voltage variations are revealed first. We focus on how these two factors influence the parameters of the delay model. According to these phenomena, a new extension based on logical effort model is proposed and the consideration to temperature and supply voltage variations is included. Finally, a simulation and analysis flow is established and the validation of the proposed model is shown.

In Chapter 4, we provide some application scenarios of the proposed extended model in different situations and under distinct temperature and supply voltage conditions. These examples can help designers to understand how to perform circuit estimation and optimization by the proposed model. Also, the circuit design flow with proposed extended logical effort model is presented in this chapter. How to utilize the proposed model with the thermal simulator in the circuit design flow is described clearly through the flowchart.

In Chapter 5, the conclusion of our research in this thesis and the future works for the improvement are presented.

Chapter 2

Overview of Logical Effort

2.1 RC Delay Model

As we introduced in Chapter 1, an accurate timing analysis can help designers to handle the arrangement of transistors or logic gates more confidently and can be used to assist in performance, power, and area optimizations. The RC delay model provides a useful method to estimate the delay of a gate without complex or time-consuming circuit simulation. It is commonly used in digital integrated circuits to model long wires, transmission gates, and pass transistor chains [20].

The RC delay model treats transistors as switches in series with resistors. Figure 2.1 shows equivalent RC circuit models for NMOS and PMOS transistors. Although the transistor has complex nonlinear current-voltage characteristics practically, it can be approximated to the average current delivered by the transistor. The capacitances in Figure 2.1 represent gate and diffusion capacitances, and the scales of the resistance and the capacitance depend on the size of the transistor. If the transistor has fixed length, it will have smaller resistance and bigger capacitance when the transistor has bigger width. Based on the simple equivalent RC delay model, the propagation delay of the logic gate can be estimated.

g

s d d

g

s

Figure 2.1 Equivalent RC circuit models [2].

Figure 2.2 shows a conceptual model of a CMOS logic gate. As shown in the figure, a CMOS logic gate consists of the PMOS pull-up network and the NMOS pull-down network. Parallel and series transistors in each network can be combined like conventional resistors, the gate capacitance and the diffusion capacitance construct input capacitance and the parasitic capacitance, and the load capacitance is usually the input capacitance of the next CMOS logic gate. In this figure, Rup and

R

down represent the pull-up and pull-down resistance, Cin, Cp, and Cout are the input, parasitic, and load capacitance.

PMOS Pull-up network

NMOS Pull-down

network

Inputs Output

Inputs

Cin Cp Cout

Output Rup

Rdown

Figure 2.2 Conceptual model of a CMOS logic gate.

According to the logic levels at the inputs, the output of the CMOS logic gate is driven “high” or “low” when Cp and Cout are charged by Rup or discharged by Rdown. Based on this conception, the propagation delay of the logic gate can be estimated as the RC product of the effective resistance and the parasitic and load capacitances.

Since the delay of the CMOS logic gate can be estimated through simple RC delay model, the delay of a logic path can also be obtained by summing up the delay of each stage. Furthermore, the basic performance estimation of the integrated circuits can be accomplished.

2.2 Logical Effort Model

In a complete circuit design, there will be some critical paths needing most attention of designers to ensure that whole circuit can meet the performance requirement. Moreover, quick delay estimation is necessary for designing these critical paths. The method of “Logical Effort Delay Model” allows designers to quickly estimate and optimize single paths by modeling equivalently delay time.

Through this simple hand-calculated method, designers can do timing evaluation with less effort and the design cycle time can be reduced efficiently.

In 1999, Sutherland, Sproull, and Harris wrote a book to introduce the theory of logical effort delay model [21]. The method of logical effort is founded on a simple model of the delay through a single CMOS logic gate. The conception is derived from the RC delay model as shown in Figure 2.3.

Figure 2.3 An illustration of the RC delay model of a CMOS logic gate.

Based on RC delay model, the delay of the logic gate can be expressed as

( )

where dabs is the absolute delay, κ is a constant, R is the pull-up or pull-down resistance, Cin, Cout and Cp are the input, load and parasitic capacitances, Rt, Cint and

C

pt are the resistance, input capacitance and parasitic capacitance of different logic gate templates, and α is a scale factor [21]. In the final form of the derivation, the

scale factor α is hidden in Cin. It means that all values of Rt, Cint, and Cpt are unrelated to the size of the logic gate, they only depend on what kind of logic gate it is, and only the values of Cin and Cout depend on the size of the logic gate.

According to the final form of above equation, the delay equation of logical effort delay model can be defined as

(

where τ is the basic delay unit, g, h, and p are the logical effort, electrical effort or fanout, and parasitic delay.

From equation (2.2), the definitions of these parameters are

, , ^{t int out}, and ^{t pt}

where Rinv and Cinv are resistance and input capacitance of an inverter template. Also, the values of τ, g, and p only depend on the topology of the logic gate, not the size of the logic gate; only the value of h depends on the ratio of size between loading and the characterized logic gate.

For a clearer interpretation, Table 2.1 shows the values of g of different gate types, assuming the ratio of PMOS transistor width to NMOS transistor width in the inverter is 2.

Table 2.1 Logical effort g of common gates.

In addition to estimate the delay, logical effort is also used to optimize an

N-stage logic path. Here we will introduce some factors first.

z Stage effort: f=gh.

z Path logical effort:

G = ∏ g

_i^. z Path branching effort:

B = ∏ b

_i^. z Path electrical effort: ^out

in

Because the sum of a set of numbers is minimized by choosing all the numbers to be equal, the path delay is minimized when each stage bears the same stage effort

ˆ

1/^N

f = g h

i i

= F

. (2.4)

According to equation (2.4), the minimum path delay will be performed when the input capacitance of each gate are

ˆ

ⁱ

.

Based on above simple equations, designers can easily manage the logic paths arrangement and obtain the optimized path delay. Actually, evaluating the exact delay of the logic paths is not the most worthful use of this model because there are many powerful CAD tools can do more precise timing verification. But this simple hand-calculated model is accurate enough to do basic performance prediction in a short time. Furthermore, using this simple model to derive the best logic gate arrangement for minimum path delay is the primary contribution indeed.

2.3 Design Example

There are two key purposes of logical effort model:

1. Estimate the delay of logic paths simply and quickly.

2. Find out the best arrangement of logic paths for minimum delay.

The following is an example for how to use logical effort model.

Example:

Figure 2.4 shows an example logic path to explain how to use logical effort model. The initial NOR2 gate presents a load of 5λ of transistor width on the input

and the output load is equivalent to 225λ of transistor width. How to estimate the minimum delay of the path from A to B and how to choose transistor sizes to achieve this delay?

Figure 2.4 An example logic path.

Solution:

The number of stages N = 3, and path branching effort B = 2×3 = 6.

gnor2 = 5/3, gnand3 = 5/3, and gnand2 = 4/3.

→ Path logical effort G = (5/3)×(5/3)×(4/3) = 100/27.

Path electrical effort H = (2x/5)×(3y/2x)×(225/3y) = 225/5 = 45.

→ Path effort F = G×B×H = 1000.

The delay of a gate d = f+p.

The path delay is minimum when each stage has the same stage effort

→

f ^ˆ =

^N

F =

³

1000 10 =

.

pnor2 = 2, pnand3 = 3, and pnand2 = 2.

→ Path parasitic delay P = 2+3+2 = 7.

The minimum path delay

D = N × + = × f ^ˆ P 3 10 7 37 + =

in unit of

τ.

Decide the transistor sizes:

ˆ (

_out

/

_in

) / f

f = g h × = g × C C

→

C

_in

= ( g C ×

_out

) ^ˆ

.

→ y = [(4/3)×225]/10 = 30, and x = [(5/3)×(30×3)]/10 = 15.

If

µp:µn = 1:2

→ Wp:Wn in NAND2 gate is 15:15.

→ Wp:Wn in NAND3 gate is 6:9.

Figure 2.5 shows the recommended solution of this example through logical effort delay model.

A 225

B N: 1P: 4

N: 9P: 6

P: 15 N: 15 x

5

y

Figure 2.5 The recommended solution of the example.

2.4 Related Research

Because of the simplicity and clarity of logical effort model, many studies have been presented to improve the accuracy of logical effort model to adapt to different design conditions. The effects of a linear input transition time and wiring RC delay is introduced in [22] and the simulated value of g and p in 0.18um process also been shown. A modified logical effort model, which accounts for the behavior of series connected MOSFET structure, switching input transition time, and internodal charges, is presented in [23]. And reference [24] introduces an extension of the logical effort model that considers the I/O coupling capacitance and the input ramp effect.

Furthermore, logical effort delay model has been used to develop new algorithms for designing circuits and been applied in some CAD tools. Based on logical effort model, reference [25] presented an algorithm which can produce the optimum fanout tree solution if the fanout tree topology is restricted to a chain of buffers. Also, a new algorithm to approach to delay-optimal mapping for solving the load-distribution problem based on the principle of logical effort is presented in [26].

All of the above are some examples of a lot of researches about logical effort model. However, the modified logical effort model been presented before do not mention how to handle temperature and supply voltage variations appropriately.

Therefore, we hope to extend the simple logical effort model and take temperature and supply voltage into account. In Chapter 3, how these two factors influence the parameters of logical effort model will be discussed. According to these phenomena, a new extension based on logical effort model will be proposed subsequently.

Chapter 3

Logical Effort Model Extension

3.1 Effects of Temperature and Supply Voltage Variations

In Chapter 2, it has been shown that logical effort delay model is expressed as

d

abs

=τ(gh+p). In this model, τ and h are constant in each process, but g and p will be

impacted by temperature and voltage variations since they are functions of effective resistance and capacitance of the logic gate. In order to understand how temperature and supply voltage variations affect the logical effort model, we establish a test circuit as Figure 3.1 to imitate a real logic path [2]. Gate A and B are used to shape the input slope, gate C is the gate being characterized, gate D and E are the load, and h is the fanout.

Figure 3.1 Test circuit for calibrating the logical effort model.

Based on the equation dabs

=τ(gh+p), it can be rewritten as (3.1).

d

abs

= τ(gh + p) = τgh + τp.

(3.1)

According to (3.1), we utilize the test circuit, change h from 1 to 8, and then obtain the curve of delay time dabs vs. fanout h as shown in Figure 3.2. In Figure 3.2, the straight line is the linear regression trendline of the curve of dabs vs. h, and the equation

y=mx+b is the linear regression equation. Matching Figure 3.2 with (3.1),

the slope of the curve is τg, and then we define the value of g is 1 under typical temperature and supply voltage conditions. τ is a constant in each process.

90nm Process, 1V, 25C

Figure 3.2 The curve of delay vs. fanout and the linear regression trendline.

Under different temperature and supply voltage conditions, we can plot the curves of delay time dabs vs. fanout h as shown in Figure 3.3 and other charts with different values of supply voltage. The slope τg of each curve is different under different conditions and τ is a constant in each process, thus we can obtain distinct values of logical effort g with different temperatures and supply voltages as shown in Table 3.1. According to the definition of g mentioned in Chapter 2, these values describe temperature and supply voltage effects on RC delay of the logic gate practically.

90nm Process, Supply Voltage = 1V

0

Figure 3.3 Simulated values of delay time with different temperature.

Table 3.1 Simulated values of g with different temperatures and supply voltages.

(In 90nm Process)

g 1V 0.9V 0.8V 0.7V 0.6V 0.5V

-50°C

0.9483 1.0421 1.1428 1.3638 1.7770 2.8651

-25°C

0.9611 1.0571 1.1608 1.3731 1.7701 2.7500

0°C

0.9792 1.0736 1.1799 1.3887 1.7751 2.6747

25°C 1.0000

(Def.) 1.0888 1.2036 1.4096 1.7871 2.6227

50°C

1.0250 1.1053 1.2326 1.4346 1.8039 2.5876

75°C

1.0509 1.1292 1.2688 1.4637 1.8258 2.5632

100°C

1.0764 1.1497 1.3030 1.4958 1.8484 2.5475

125°C

1.1019 1.1750 1.3399 1.5164 1.8724 2.5373

Based on Table 3.1, we can plot the 3-D graphs of the value of g and 1/g versus temperature and supply voltage as Figure 3.4 and Figure 3.5. According to these graphs, we can utilize linear regression to perform curve fitting and derive the new extended logical effort model as a simple linear format from 1/g because the shape of the surface in Figure 3.5 is flatter.

Figure 3.4 The values of g with different values of temperature and supply voltage.

Figure 3.5 The values of 1/g with different values of temperature and supply voltage.

3.2 Derivation of Extended Logical Effort Model

Based on the definition of g, we rewrite the equation of g as

t int DD in

where Reff and Cin are effective resistance and input capacitance of the gate, VDD is the supply voltage, and Id is the saturation current. As shown in Table 3.2, according to simulation results, k is close to a constant under different temperature and supply voltage conditions.

Table 3.2 Simulated values of k with different temperatures and supply voltages.

(In 90nm Process)

k=g*Id/(Vdd*Cin)

(10^12) 1V 0.9V 0.8V 0.7V 0.6V 0.5V -50°C

0.1859 0.1845 0.1778 0.1786 0.1826 0.2031

-25°C

0.1850 0.1844 0.1787 0.1791 0.1831 0.2009

0°C

0.1847 0.1840 0.1790 0.1794 0.1834 0.1988

25°C

0.1843 0.1826 0.1791 0.1792 0.1830 0.1963

50°C

0.1840 0.1807 0.1790 0.1785 0.1819 0.1935

75°C

0.1831 0.1793 0.1791 0.1774 0.1804 0.1906

100°C

0.1815 0.1767 0.1781 0.1760 0.1784 0.1877

125°C

0.1793 0.1742 0.1770 0.1729 0.1763 0.1850

3.2.1 Saturation Current I

d

Table 3.3 shows the values of saturation current Id under different temperature and supply voltage conditions in 90nm process. According to this table, we can observe that the factors of temperature and voltage influence Id enormously. Thus, Id

is the key factor for deriving the extended logical effort model.

Table 3.3 Simulated values of Id with different temperatures and supply voltages.

(In 90nm Process)

I

d

(uA) 1V 0.9V 0.8V 0.7V 0.6V 0.5V

-50°C

154.6342 125.8323 98.2861 72.2842 48.3234 27.2964

-25°C

152.0374 124.1019 97.3316 72.0113 48.6453 28.1285

0°C

149.5167 122.3091 96.1961 71.4747 48.6730 28.6917

25°C

146.9099 120.3315 94.8045 70.6507 48.4272 29.0279

50°C

144.1031 118.0980 93.1331 69.5606 47.9594 29.1926

75°C

141.0290 115.5845 91.2000 68.2549 47.3333 29.2411

100°C

137.6620 112.8041 89.0504 66.7967 46.6112 29.2204

125°C

134.0091 109.7944 86.7418 65.2486 45.8458 29.1665

Because of the effect of velocity saturation, the saturation current model is expressed as Id

=KW(V

gs

-V

t

), where K is the drive ability factor, W is the transistor

width, and Vt is the threshold voltage [27]. In this equation, K and Vt are temperature and supply voltage-dependent. In order to perform a simple extended logical effort model, we try to express K and Vt as simple linear functions of temperature t and supply voltage VDD. Figure 3.6 and Figure 3.7 describe the temperature and supply voltage effects on K and Vt.

0 100 200 300 400 500 600

-75 -50 -25 0 2 5 50 75 1 00 125 150

Temperature (C)

K ( A /V m )

1V 0 .9 V 0.8V

0.7V 0 .6 V 0.5V

Figure 3.6 The values of K with different temperatures and supply voltages.

0

Figure 3.7 The values of Vt with different temperatures and supply voltages.

3.2.2 Drive Ability Factor K

Based on Figure 3.6, we can observe that K is close to a linear function of temperature t with different VDD. Thus, we assume K as the equation K=mt+b, where

m is the slope and b is the intercept. With different supply voltages, we can obtain

different values of m and b. Figure 3.8 and Figure 3.9 show the simulation results of

m and b in 90nm process. According to simulation results shown as Figure 3.8, b can

be rewritten as an approximate equation b=mKV

V

DD

+K

0, where mKV and K0 are constant. With Figure 3.9, since the value of t is in a range of -50~125, the effect of the value of m is much smaller than b, thus we replace m with the average value mKt. The final approximate equation of K is expressed as

K=m

Kt

t+m

KV

V

DD

+K

0. (3.3)

b (Intercept)

Figure 3.8 The values of b with different supply voltages.

m (Slope)

Figure 3.9 The values of m with different supply voltages.

3.2.3 Threshold Voltage V

t

V

t is a linear function of temperature t and the effect of supply voltage VDD on Vt

is small. In order to simplify the extended logical effort model, the effect of VDD on Vt

is ignored and Vt is expressed as the equation

V

t

=m

Vt

t+V

t0 (3.4) where mVt and Vt0 are constant.

3.2.4 Input Capacitance C

in

According to simulation results, we observed that the effects of temperature and voltage on Cin are much smaller than on Id. In order to simplify the extended logical effort model, the value of Cin is assumed as a constant in the proposed model.

Table 3.4 Simulated values of Cin with different temperatures and supply voltages.

(In 90nm Process)

C

in

(fF) 1V 0.9V 0.8V 0.7V 0.6V 0.5V -50°C

0.7886 0.7895 0.7898 0.7887 0.7840 0.7701

-25°C

0.7897 0.7904 0.7903 0.7888 0.7836 0.7703

0°C

0.7925 0.7929 0.7925 0.7905 0.7850 0.7721

25°C

0.7970 0.7971 0.7963 0.7939 0.7881 0.7756

50°C

0.8028 0.8026 0.8015 0.7987 0.7927 0.7806

75°C

0.8094 0.8089 0.8076 0.8045 0.7984 0.7866

100°C

0.8163 0.8157 0.8142 0.8109 0.8047 0.7933

125°C

0.8234 0.8226 0.8209 0.8175 0.8113 0.8002

Based on previous analysis results, the equation of logical effort g can be rewritten as (3.5) and (3.6).

( )

After replacing K and Vt in the formula of 1/g with these equations, we simplify the formula by Taylor expansion.

A Taylor expansion of f(x) at x=a is voltage VDD through Taylor expansion:

1

f V

( _DD)

f a

( )

f a V

'( )( _DD

a

)

A t V

( ) _DD

B

( )

and

For presenting a simple linear extended logical effort model and after evaluating

A(t) and B(t), the final extended model of g is presented as the following formula:

1/g = (m

t

t+b

t

)V

DD

+C

(3.11)

3.3 Analysis Flow

To sum up above steps, Figure 3.10 shows an overview of the simulation and analysis flow.

A

Establish a Test Circuit

D

Saturated Transistor Simulation for Id and Vt C

Capacitance Simulation for Input Capacitance Cin of

An Inverter

Compare Calculated Results with Simulated Results and Prove the

Accuracy of Extended Model

Figure 3.10 An overview of the simulation and analysis flow.

The following is the statement of Figure 3.10:

A. Select an inverter with suitable transistor size as a unit inverter, and then establish a 5-stage inverter chain as the test circuit to imitate a real logic path.

B. Obtain simulated values of delay dabs with different values of fanout h through the test circuit. Then evaluate the simulated values of τ, g, and p by the equation dabs

=τ(gh+p) and the curves of d

abs vs. h under different temperature and supply voltage conditions.

C. Simulate with a unit inverter, give input 0 and 1, and then obtain the average value of input capacitance Cin under different temperature and supply voltage conditions.

D. Simulate with each PMOS and NMOS transistor, and obtain the values of saturation current Id and threshold voltage Vt under different temperature and supply voltage conditions.

E. Use the data received from above steps, calculate the values of equation

1/g=(m

t

t+b

t

)V

DD

+C, and obtain the calculated values of g.

F. Compare the calculated values of g with simulated values, then, we can prove that the proposed extended model is accurate enough.

A new extended logical effort model which takes temperature and voltage into account has been established. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions with minimum effort by (2.2), (2.4), (2.5), and (3.11). It can avoid a serious misestimate induced by temperature and supply voltage variations.

Additionally, because the parasitic delay p will be dominated by the style and area of layout and wire routing, we don’t discuss these issues here.

3.4 Validation

Figure 3.11and Figure 3.12 show the comparison between simulated and calculated values of g and 1/g in 90nm process in 2-D and 3-D charts. The calculated value of g is obtained from (3.11). In Figure 3.11, we can find that the calculated values are close to the simulated values. In 90nm process, the transistors work approaching triode region at 0.5V and the inaccuracy of the simulation tools inherently are the occasions of the big difference between calculated and simulated values at 0.5V. In Figure 3.12, we provide a 3-D chart to emphasize the linear relationship between 1/g and temperature and voltage. After validation, the accuracy of this simple extended logical effort model can achieve about 90%.

0.5 1 1.5 2 2.5 3

-75 -50 -25 0 25 50 75 100 125 150

Temperature (C)

g

0.5V

0.6V

0.7V 0.8V 0.9V 1.0V

Figure 3.11 The comparison between simulated and calculated values of g in 2-D.

Simulated values are solid lines and calculated values are dotted lines.

Figure 3.12 The comparison between simulated and calculated value of 1/g in 3-D.

Simulated values are solid lines and calculated values are dotted lines.

The simulated values of logical effort g are shown in Table 3.1, and the calculated values of logical effort g’ are shown in Table 3.5. Table 3.6 demonstrates the variation between the calculated value g’ and the simulated value g. All statistics shown in these tables are in 90nm process.

Table 3.5 Calculated values of g’ with different temperatures and supply voltages.

(In 90nm Process)

g’ 1V 0.9V 0.8V 0.7V 0.6V 0.5V

-50°C

0.9346 1.0415 1.1761 1.3505 1.5858 1.9203

-25°C

0.9596 1.0695 1.2078 1.3871 1.6290 1.9731

0°C

0.9860 1.0990 1.2412 1.4257 1.6747 2.0289

25°C

1.0139 1.1302 1.2766 1.4666 1.7230 2.0880

50°C

1.0434 1.1632 1.3140 1.5098 1.7741 2.1506

75°C

1.0747 1.1982 1.3537 1.5556 1.8284 2.2171

100°C

1.1079 1.2353 1.3959 1.6044 1.8861 2.2879

125°C

1.1432 1.2748 1.4407 1.6563 1.9476 2.3633

Table 3.6 The variation between simulated and calculated values of g.

(In 90nm Process)

(g’-g)/g 1V 0.9V 0.8V 0.7V 0.6V 0.5V -50°C

-1.4429% -0.0555% 2.9105% -0.9751% -10.7603% -32.9781%

-25°C

-0.1573% 1.1733% 4.0485% 1.0204% -7.9686% -28.2516%

0°C

0.7012% 2.3666% 5.1941% 2.6654% -5.6585% -24.1423%

25°C

1.3902% 3.8021% 6.0639% 4.0418% -3.5891% -20.3865%

50°C

1.7992% 5.2345% 6.6090% 5.2402% -1.6493% -16.8856%

75°C

2.2666% 6.1049% 6.6884% 6.2844% 0.1446% -13.5008%

100°C

2.9255% 7.4494% 7.1243% 7.2608% 2.0375% -10.1914%

125°C

3.7496% 8.5011% 7.5269% 9.2208% 4.0170% -6.8574%

Chapter 4

Design Procedure and Application Scenarios

4.1 Circuit Design Flow with Proposed Model

In Chapter 3, the effects of temperature and supply voltage variations are revealed and the logical effort model extension for temperature and voltage variations is proposed. In this section, the circuit design flow with proposed model will be interpreted clearly.

As discussed in previous chapters, the increasing transistor density and operation frequency of the integrated circuits will induce the raising chip temperature. And the temperature variation will influence the speed of the circuits and may cause incorrect

As discussed in previous chapters, the increasing transistor density and operation frequency of the integrated circuits will induce the raising chip temperature. And the temperature variation will influence the speed of the circuits and may cause incorrect

在文檔中 針對溫度及電壓變異所做之Logical Effort Model之延伸 (頁 16-0)