This dissertation is divided into four chapters. The contents in each chapter are described as follows.
In chapter 1, the potential memory devices about nonvolatile memory (NVM)、
conventional Flash、SONOS and SOHOS devices are introduced in this chapter.
In chapter 2, this section focus on the basic program and erase mechanisms of
Flash memory device.
In chapter 3, the SOHOS structure with HfO2 trapping layer , oxynitride and oxide as tunnel oxide layer is proposed in this section. Finally, compare the oxynitride layer with convention oxide layer, the device characteristics will be discussed between two different tunnel oxide process conditions.
In chapter 4, this section includes the conclusions and the future work of this study..
Table 1.1: Performance Comparison between volatile memory (DRAM and SRAM) and nonvolatile memory (Flash, FRAM, MRAM and phase change memory) devices. Among the nonvolatile memories, Flash memory is the only memory compatible with the current CMOS process flow. Overall, the Flash memory exhibits the best performance except for the disadvantages of high programming voltage and slow program/erase speed.
Fig1-1: Schematic cross section of the conventional floating gate nonvolatile memory device. Poly-Si floating gate is used as the charge storage element.
Fig1-2: Schematic cross section of ETOX device.
n+ n+
p+ n－
LDD anti-LDD
Si-Substrate Tunnel Oxide Layer
Blocking Oxide Floating Gate
Control Gate
Drain Source
Fig1-3: I-V curves of a floating gate device when there is no charge stored in the FG (“1”-curve) and when a negative charge Q is stored in the FG (“0”-curve).
“1” “0”
VT ID
VGS
FC
TH Q C
V =− /
∆
VT0
Fig1-4: Schematic cross section of the SONOS nonvolatile memory device. The nitride layer is used as the charge-trapping element.
Fig1-5: Energy band diagrams of SONOS Flash memory. Large φo will block electron leakage effectively and improve retention time.
Et φo
EC
EV
(“2”)
(“1”)
N+ gate
control oxide trapping
layer tunnel
oxide φ1:3.1eV
Si-Substrate Tunnel Oxide Layer
Blocking Oxide Si3N4 Trapping Layer
Control Gate
Drain Source
ONO
CHAPTER 2
Basic Principles of Nonvolatile Memory
2.1 Program/Erase Operation Mechanisms
Most of operations on novel nonvolatile memories, such as nanocrystal and SONOS memories are base on the concept of Flash memory. If charge has to be stored in a bit of the memory, there are some different procedures. The threshold voltage shift of a Flash memory transistor can be written as [31-32]:
FC
TH C
V =− Q
∆ ……….eq. 2-1
where Q is a negative charge stored in the FG, and CFC is the capacitances
between the floating gate (FG) and control gate. The threshold voltage of the memory cell can be altered by changing the amount of charge present between the gate and the channel, corresponding to the two states of the memory cell, i.e., the binary values (“1” and “0”) of the stored bit. Figure 1-3 shows the threshold voltage shift between two states in a Flash memory. Regarding a nonvolatile memory, it can be “written”
into either state “1” or “0” by either “programming” or “erasing” operation, which are decided by the definition of memory cell itself. There are many solutions to achieve
“programming” or “erasing”. In general, hot carrier electron injection (HCEI), F-N tunneling and band to band tunneling (BTBT), are three kinds of common operation mechanism employed in novel nonvolatile memories. The three mechanisms will lead difference characteristics for nonvolatile memories.
2.1.1 Channel Hot-Electron Injection (CHEI)
The physical mechanism of CHEI is relatively simple to understand qualitatively.
An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons).
At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100kV/cm [33]. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. Electrons are “heated” by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges. Figure 2-1 shows schematic representation of CHEI MOSFET and the energy-distribution function with different fields. On the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection rarely is employed in nonvolatile memory operation. For an electron to overcome this potential barrier, three conditions must hold [34].
(1) Its kinetic energy has to be higher than the potential barrier.
(2) It must be directed toward the barrier.
(3) The field in the oxide should be collecting it.
During programming, the positive voltages applied to the gate and drain while the source is grounded. These voltages generate a lateral and vertical electric field along the channel. The electrons will move from the source to the drain and be accelerated by high lateral field near the drain junction in the channel. Once the
electrons gain enough energy, they can surpass the energy barrier of the oxide layers and inject into trapping layer and be trapped. The current density of CHEI is expressed as
HereI is the channel current andds A is a constant. d
2.1.2 Tunneling Injection
Tunneling mechanisms are demonstrated in quantum mechanics. Basically, tunneling injection must to have available states on the other side of the barrier for the carriers to tunnel into. If we assume elastic tunneling, this is a reasonable assumption due to the thin oxide thickness involved. Namely, no energy loss during tunneling processes. The tunneling probability, depending on electron barrier height (ϕ(x)), tunnel dielectric thickness ( d ), and effective mass ( me ), is express as
) )
Tunneling through the oxide can be attributed to different carrier-injection mechanisms. Which process applies depends on the oxide thickness and the applied gate field or voltage. Direct tunneling (DT), Fowler-Nordheim tunneling (FN), modified Fowler-Nordheim tunneling (MFN) and trap assistant tunneling (TAT) are the main programming mechanisms employed in memory [35-38].
2.1.2-(a) Direct Tunneling (DT)
For nanocrystal memories, the control-gate coupling ratio of nanocrystal memory devices is inherently small [39]. As a result, FN tunneling cannot serve as an efficient write/erase mechanism when a relatively thick tunnel oxide is used, because the strong electric field cannot be confined in one oxide layer. The direct tunneling is employed in nanocrystal memories instead. In the other hand, the direct tunneling is more sensitive to the barrier width than barrier height, two to four orders of magnitude reduction in leakage current can still be achieved if large work function metals, such as Au or Pt [40].
2.1.2-(b) Fowler–Nordheim Tunneling (FN)
The Fowler–Nordheim (FN) tunneling mechanism occurs when applying a strong electric field (in the range of 8~10MV/cm) across a thin oxide. In these conditions, the energy band diagram of the oxide region is very steep. Therefore, there is a high probability of electrons’ passing through the energy barrier itself. Using a free-electron gas model for the metal and the WKB (Wentzel-Kramers-Brillouim) approximation for the tunneling probability [41], one obtains the following expression for current density [42]:
⎥⎥
of the electron in the forbidden gap of the dielectric, h is the Planck’s constant, q is the electronic charge, and Eox is the electric field which is defined as the applied voltage divided by total thickness of the tunnel and control oxide. Figure 2-2 shows the F-N tunneling mechanism.
2.1.2-(c) Modified Fowler–Nordheim Tunneling (MFN)
Modified Fowler–Nordheim tunneling (MFN) is similar to the traditional FN tunneling mechanism, yet the carriers enter the nitride at a distance further from the tunnel oxide-nitride interface. MFN mechanism is frequently observed in SONOS memories. The SONOS memory is designed for low-voltage operation (<10V, depending on the Equivalent oxide thickness), a relatively weak electrical field couldn’t inject charges by DT or FN tunneling mechanism. Figure 2-3 shows the MFN tunneling mechanism.
2.1.2-(d) Trap Assistant Tunneling (TAT)
The charge storage mediums with many traps may cause another tunneling mechanism. For example, the charges tunnel through a thin oxide and arrive to the traps of nitride layer at very low electrical field in SONOS systems. During trap assisted injection the traps are emptied with a smaller time constant then they are filled. The charge carriers are thus injected at the same distance into the nitride as for MFN injection. Because of the sufficient injection current, trap assistant tunneling may influence in retention [43]. Figure 2-4 shows the TAT tunneling mechanism.
2.1.3 Band to Band Tunneling (BTBT)
In MOS structures, band-to-band tunneling typically occurs at high source or drain voltage and low gate voltage. In Flash memory devices, these conditions take place in cells under erase operations, or in unselected cells sharing the same bit line with a cell under programming. BTBT contributes to the so called Gate Induced Drain Leakage current (GIDL) [44-45] , which can be a significant fraction of the subthreshold drain leakage current and can compromise proper functioning of the substrate bias generators.
Band to band tunneling application to nonvolatile memory was first proposed in 1989. I. C. Chen and et al. demonstrated a high injection efficiency (~1%) method to programming EPROM devices [46]. Band-to-band Tunneling (BTBT) process occurs in the deeply depleted doped surface region under the gate to drain or gate to source overlap region. Figure 2-5 shows the band diagram of a MOS and illustrates BTBT mechanism. In this condition, the band-to-band tunneling current density is expressed as
2.1.3-(a) Band to Band Hot Electron Tunneling Injection
When band-bending is higher than the energy gap of the semiconductor, the tunneling electron from the valence band to the conduction band becomes significant.
The mechanism is at the condition for positive gate voltage and negative drain voltage.
Hence, the hot electrons are injected through the tunnel oxide and then recombine the stored holes as shown in Figure 2-6.
2.1.3-(b) Band to Band Hot Hole Tunneling Injection
The injection is applied for p-type substrate nonvolatile memory device. The mechanism is at the condition for negative gate voltage and positive drain voltage.
Hence, the hot holes are injected through the tunnel oxide and then recombine the stored electrons as shown in Figure 2-7.