Chapter 1 Introduction
1.3 Organization of This Thesis
In the remaining part of the thesis, Chapter 2 introduces the bus model, the power consumption in the buses and the concepts of bus encoding. In Chapter 3, we introduce the existing bus encoding schemes including BI, BITS, hihrTS and EXODUS schemes.
In Chapter 4, we propose a new encoding scheme – Dynamic BI-XNOR, which dynamically adapts to data patterns and applies the identity, invert and xnor bus encoding operations accordingly. In Chapter 5, we present the simulation results and related analyses. In Chapter 6, we compare all the schemes realized in RTL and estimate the power consumption. In Chapter 7, we use CoWare Platform Architect to build an ARM-Based SoC virtual platform and implement all encoding schemes. The study case is IEEE 802.16e baseband transmitter. Finally, we summarize our conclusions in Chapter 8.
Chapter 2 Background
In this section, we briefly introduce the bus model with intrinsic capacitances. The intrinsic capacitances include self capacitances and coupled capacitances. They involve in the power dissipation when the data is transmitted in the bus lines. Finally we introduce the concepts of bus encoding.
2.1 Bus Model
The general bus model is shown in Fig.2.1. The processor fetches instructions from the memory and reads data from or writes data into memory or register through bus lines.
Processor .. Memory
. . .
Register
. . . . .
Data R/W Instruction Read
Data R/W
Fig.2.1 General Bus Model
2.2 Bus Model with Self and Coupling Capacitances
Fig.2.2 shows the bus model with self capacitances and coupling capacitances. A self capacitance (Cs) is generated between a bus line and ground. A coupling capacitance (Cc) is generated between any two adjacent bus lines.
Bus Lines
Cc
Cc Cc Cs
Cs Cs
Fig.2.2 Bus Model with Self and Coupling Capacitances
2.3 Bus Transitions
Bus transitions (i.e., signal transitions or bit transitions) include two types – self
transition occurs in bus line 2 (0 to 1) and another occurs in bus line 4 (1 to 0). Fig.2.4 shows correlative transitions in a bus model. A correlative transition occurs between bus line 2 and bus line 3 since the bus line 2 switches from 0 to 1 and the bus line 3 switches from 1 to 0.
Self Transition Cc
Cc Cc Cs
Cs Cs Bus Line 2
Bus Line 3
Bus Line 4 Bus Line 1
Self Transition
Fig.2.3 Self Transitions
Correlative Transition Cc
Cc Cc Cs
Cs Cs Bus Line 2
Bus Line 3
Bus Line 4 Bus Line 1
Fig.2.4 Correlative Transitions
2.4 Power Dissipation
Power dissipation in buses is related to the intrinsic capacitances of the bus lines (i.e., self and coupling capacitances) and the bus transitions occurring in the wires. Fig.2.5 [1]
shows the charging and discharging on the self capacitances when a self transition occurs.
-Fig.2.5 (a) Charging Event of Self Capacitance (b) Discharging Event of Self Capacitance
Table 2.1 shows the power analysis for self transitions. The power dissipation of both events is derived from the equation:
2
Fig.2.6 shows the charging and discharging scenario on the coupling capacitances when a correlative transition occurs. [1]
Cc
Fig.2.6 Charging / Discharging Events of Coupling Capacitance (a)10 to 01 (b)01 to 10
Since the relative change in the potential difference of the capacitance is 2V , and dd a correlative transition involves in two self transitions, the power dissipation caused by a correlative transition is expressed as
So we obtain the averaged power dissipation of the bus lines per bus cycle
2 2 2
γ S is the number of averaged self transitions per bus cycle.
γC is the number of averaged correlative transitions per bus cycle.
Thus to lower bus transitions will result in the reduction of power dissipation.
2.5 Bus Encoding
Bus encoding means to encode the original data patterns so that the encoded patterns have fewer bus transitions than that of the original patterns. Above all, the encoded data must be able to be decoded to the original data patterns correctly. Fig.2.7 shows the model of bus encoding.
Encoder N-bits
Bus Lines Decoder
. . . .
. . . . .
. . .
. . . . Data Transmission
D(t) E(t) E(t) D(t)
Fig.2.7 Bus Encoding
Bus encoding aims at the reduction of self transitions. Since every correlative transition involves in two self transitions, the reduction of self transitions will naturally result in the reduction of correlative transitions. In this thesis, we use an 8-bit bus as an encoding set.
Chapter 3
Existing Encoding Schemes
In this section, we introduce four known bus encoding schemes in detail. They are bus invert (BI), transition signaling combined with bus inverter (BITS), half-identity half-reverse and transition signaling (hihrTS) and exclusive or-xnor duo scheme (EXODUS). For all these encoding schemes, the first data pattern D(0) is not encoded. So the first encoded pattern E(0) is equal to D(0). All discussions and examples are based on 8-bit wide bus. Finally we will observe these schemes and discuss their pros and cons.
3.1 BI Encoding Scheme
BI encoding scheme [2] [3] applies inverse operation to encode data patterns and an extra control bit Inv is needed to indicate the decoder how the data pattern is encoded. In the encoding process, the first pattern D(0) is not encoded so E(0) is equal to D(0). From D(1), the previous encoded pattern is compared with the current un-encoded pattern. That means, the previous encoded pattern E(t) is compared with current data pattern D(t+1). If the number of self transitions is less than or equal to four, the Inv bit is set to 0 and all bits of the current data pattern will not be changed, i.e.,
E(t+1) = D(t+1) (3.1) If the number of self transitions is greater than four, the Inv bit is set to 1 and all bits of
current data pattern will be inverted, i.e.,
E(t+1) = [D(t+1)]’ (3.2) And the Inv bit is 1. The encoding flow chart is in shown Fig.3.1.
Fig.3.1 Flow Chart of BI Encoding Scheme
Fig.3.2 shows an example of BI encoding. Fig.3.2(a) shows the data patterns of 8-bit bus to be transmitted. The first data pattern D(0) is not encoded, so we get E(0) in Fig.3.2(b). Then we compare E(0) and D(1). Since there are five self transitions between E(0) and D(1), so we invert D(1) to get E(1) in Fig.3.2(c) and its Inv bit is 1. Then we compare E(1) and D(2). Since there are three self transitions between E(1) and D(2), we obtain E(2) which is equal to D(2) in Fig.3.2(d) and its Inv bit is 0.
D(0)
Inv Inv Inv Inv
Fig.3.2 An Example of BI Encoding Scheme
Fig.3.3 shows the encoder structure of BI scheme. The first set of XOR gates compare E(t) and D(t+1) to detect if they have self transitions. If they are different the output is 1, otherwise the output is 0. The comparison results are sent to multiplexer to gather statistics and send a control bit Inv. If the number of self transitions is greater than four, the multiplexer will send an output 1, otherwise the output is 0. In the second set of XOR gates, the Inv bit indicates whether D(t+1) should be inverted or not. If the Inv bit is 1, D(t+1) will be inverted to get the encoded result E(t+1). Otherwise E(t+1) is just equal to D(t+1).
Mux
D0(t+1) E0(t)
E0(t+1)
D1(t+1) E1(t)
E1(t+1)
D2(t+1) E2(t)
E2(t+1)
D3(t+1) E3(t)
E3(t+1)
D4(t+1) E4(t)
E4(t+1)
D5(t+1) E5(t)
E5(t+1)
D6(t+1) E6(t)
E6(t+1)
D7(t+1) E7(t)
E7(t+1)
Inv
Fig.3.3 Encoder Structure of BI Scheme
Fig.3.4 shows the decoder structure of BI scheme. It’s quite easy to decode. In the set of XOR gates, the Inv bit indicates whether E(t+1) should be inverted or not. If Inv is 1, E(t+1) is inverted to get D(t+1). Otherwise D(t+1) is equal to E(t+1).
E0(t+1)
Inv
D0(t+1)
E1(t+1) D1(t+1)
E2(t+1) D2(t+1)
E3(t+1) D3(t+1)
E4(t+1) D4(t+1)
E5(t+1) D5(t+1)
E6(t+1) D6(t+1)
E7(t+1) D7(t+1)
Fig.3.4 Decoder Structure of BI Scheme
3.2 BITS Encoding Scheme
BITS encoding scheme [3] applies both XOR and inverse operations to encode data patterns. The same as BI scheme, this scheme needs an extra control bit Inv, too. E(0) is also equal to D(0). Then this scheme calculates the number of 1’s of each data pattern except D(0). If the number of 1’s is less than or equal to four,
E(t+1)＝D(t+1)♁E(t) (3.3) And the Inv bit is 0. Oppositely if the number of 1’s is greater than four,
E(t+1)＝[D(t+1)]’♁E(t) (3.4) And the Inv bit is 1. The encoding flow chart is shown in Fig.3.5.
Fig.3.5 Flow Chart of BITS Encoding Scheme
Fig.3.6 shows an example of BITS encoding. Fig.3.6(a) shows the data patterns of 8-bit bus to be transmitted. The first data pattern D(0) is not encoded, so we get E(0) in Fig.3.6(b). Then we calculate the number of 1’s in D(1). Since there are four 1’s in D(1), so E(1)＝D(1)♁E(0), as shown in Fig.3.6(c) and the Inv bit is 0. Then we calculate the number of 1’s in D(2). Since there are five 1’s in D(2), E(2)＝[D(2)]’♁E(1) as shown in Fig.3.6(d) and the Inv bit is 1.
summation of D0(t+1) to D7(t+1) and sends the control bit Inv. In the first set of XOR gates, the Inv indicates whether D(t+1) should be inverted or not. In the second set of XOR gates, D(t+1) or [D(t+1)]’ executes XOR operation with E(t) to get E(t+1).
Mux
D0(t+1)
E0(t) E0(t+1)
D1(t+1)
E1(t) E1(t+1)
D2(t+1)
E2(t) E2(t+1)
D3(t+1)
E3(t) E3(t+1)
D4(t+1)
E4(t) E4(t+1)
D5(t+1)
E5(t) E5(t+1)
D6(t+1)
E6(t) E6(t+1)
D7(t+1)
E7(t) E7(t+1)
Inv
Fig.3.7 Encoder Structure of BITS Scheme
Fig.3.8 shows the decoder structure of BITS scheme. In the first set of XOR gates, E(t+1) executes XOR operation with E(t). In the second set of XOR gates, the Inv bit indicates whether D(t+1) should be inverted or not.
E0(t+1)
E0(t)
Inv
D0(t+1)
E1(t+1)
E1(t)
D1(t+1)
E2(t+1)
E2(t)
D2(t+1)
E3(t+1)
E3(t)
D3(t+1)
E4(t+1)
E4(t)
D4(t+1)
E5(t+1)
E5(t)
D5(t+1)
E6(t+1)
E6(t)
D6(t+1)
E7(t+1)
E7(t)
D7(t+1)
Fig.3.8 Decoder Structure of BITS Scheme
3.3 hihrTS Encoding Scheme
HihrTS encoding scheme [3] applies both XOR and inverse operations to encode data patterns. Unlike BI and BITS schemes, this scheme does not need any control bit.
The encoding flow chart is in shown Fig.3.9.
E(t+1) = D(t+1)♁E(t) first bit is 0
Received data D(t+1)
Check the first bit
E(t+1) = [D(t+1)]'♁E(t) first bit is 1
Fig.3.9 Flow Chart of hihrTS Encoding Scheme
Fig.3.10 shows an example of hihrTS encoding scheme. Fig.3.10(a) shows the data patterns of 8-bit bus to be transmitted. The first data pattern D(0) is not encoded, and E(0)=D(0) as shown in Fig.3.10(b). Next, we consider data pattern D(1). Since its first bit is 0, we get E(1)＝D(1)♁E(0) except the first bit as depicted in Fig.3.10(c). Then we consider the data pattern D(2). Since its first bit is 1, E(2)＝[D(2)]’♁E(1) except the first bit as shown in Fig.3.10(d).
D(0)
Fig.3.11 shows the encoder structure of hihrTS encoding scheme. In the first set of XOR gates, D0(t+1) executes XOR operation with the other seven bits (D1(t+1) to D7(t+1)) respectively. If D0(t+1) is 1, all the other seven bits will be inverted. In the second set of XOR gates, D(t+1) or [D(t+1)’] executes XOR operation with E(t) to get the E(t+1).
D1(t+1)
E1(t) E1(t+1)
D2(t+1)
E2(t) E2(t+1)
D3(t+1)
E3(t) E3(t+1)
D4(t+1)
E4(t) E4(t+1)
D5(t+1)
E5(t) E5(t+1)
D6(t+1)
E6(t) E6(t+1)
D7(t+1)
E7(t) E7(t+1)
D0(t+1) E0(t+1)
Fig.3.11 Encoder Structure of hihrTS Scheme
Fig.3.12 shows the decoder structure of hihrTS scheme. D0(t+1) is equal to E0(t+1).
E0(t+1) D0(t+1) E1(t+1)
E1(t)
D1(t+1)
E2(t+1)
E2(t)
D2(t+1)
E3(t+1)
E3(t)
D3(t+1)
E4(t+1)
E4(t)
D4(t+1)
E5(t+1)
E5(t)
D5(t+1)
E6(t+1)
E6(t)
D6(t+1)
E7(t+1)
E7(t)
D7(t+1)
Fig.3.12 Decoder Structure of hihrTS Scheme
3.4 EXODUS Encoding Scheme
BXODUS encoding scheme [4] applies XOR-XNOR duo (XON type) or XNOR-XOR duo (XNO type) logic to encode data patterns. This scheme needs two extra control bits to indicate the decoder which encoding type the data pattern is encoded. For 8-bit wide bus data patterns, each pattern is divided into two subsets D (t+1) and M4 D (t+1) . Each subset consists of four bits and an additional control bit. For each subset, L4
the two most significant bits D (t+1) and the two least significant bits M2 D (t+1) are L2 independently encoded as follows：
XON type (XOR-XNOR duo)： XNO type (XNOR-XOR duo)：
2( 1) 2( 1) 2( ) Assume D(t+1) is 0010 and E(t) is 1101. The two MSBs of D(t+1) are expressed as D (t+1) which is equal to 00 and the two LSBs of D(t+1) are expressed as M2 D (t+1) L2
Table 3.1 shows the encoding rule of EXODUS encoding scheme. Note that it has
Table 3.1 Encoding Rule of EXODUS Encoding Scheme
Encoding Priority Group of D(t+1) Encoding Type
x01x XON
x10x XNO
xxx0 XNO
xxx1 XON
1
2
x represents don't-care bit
Fig.3.13 Flow Chart of EXODUS Encoding Scheme
Fig.3.14 shows an example of EXODUS encoding scheme. Fig.3.14(a) shows the data patterns of the 8-bit bus to be transmitted. The first encoded data E(0) is directly set to the original data pattern D(0) as shown in Fig.3.14(b). Then we divide D(1) into two subsets of four bits, which are 0101 and 1010, respectively. Since 0101 is in the group of
“x10x” and 1010 is in the group of “x01x”, we apply XNO type to 0101 and XON type to 1010. Then we get E(1) in Fig.3.14(c). The control bit of subset one is XNO and that of subset two is XON. Next, we divide D(2) into two subsets of four bits, which are 1011 and 0110, respectively. Since 1011 is in the group of “x01x” and 0110 is in the group of
“xxx0”, we apply XON type to 1011 and XNO type to 0110. Then we get E(2) in Fig.3.14(d). The control bit of subset one is XON and that of subset two is XNO.
D(0)
Ctrl Ctrl Ctrl Ctrl
Fig.3.14 An Example of EXODUS Encoding Scheme
Fig.3.15 shows the encoder structure of EXODUS encoding scheme. Multiplexer 1 decides the group of the four MSBs of D(t+1) and send a control bit CM. Multiplexer 2 decides the group of the four LSBs of D(t+1) and send another control bit CL. For the four MSBs of D(t+1), D (t+1) executes XOR operation with M4 E (t) by the first set M4 two LSBs and the two MSBs of the four MSBs have opposite operations. If CM is 1, all operations are reverse. For the four LSBs of D(t+1), CL has the same function as CM in all
Mux 1
D0(t+1) E0(t)
E0(t+1)
D1(t+1) E1(t)
E1(t+1)
D2(t+1) E2(t)
E2(t+1)
D3(t+1) E3(t)
E3(t+1)
Mux 2
D4(t+1) E4(t)
E4(t+1)
D5(t+1) E5(t)
E5(t+1)
D6(t+1) E6(t)
E6(t+1)
D7(t+1) E7(t)
E7(t+1)
CM
CL
Fig.3.15 Encoder Structure of EXODUS Scheme
Fig.3.16 shows the decoder structure of EXODUS scheme. In the first set of XOR gates, E(t+1) executes XOR operation with E(t). In the second set of XOR gates, CM indicates the four MSBs whether D(t+1) should be inverted or not and CL indicates the four LSBs whether D(t+1) should be inverted or not. The inversion gates denote that the two MSBs and the two LSBs of each 4-bit subset have opposite operations.
CM
CL
E1(t+1)
E1(t)
D1(t+1)
E2(t+1)
E2(t)
D2(t+1)
E3(t+1)
E3(t)
D3(t+1)
E4(t+1)
E4(t)
D4(t+1)
E5(t+1)
E5(t)
D5(t+1)
E6(t+1)
E6(t)
D6(t+1) E0(t+1)
E0(t)
D0(t+1)
E7(t+1)
E7(t)
D7(t+1)
Fig.3.16 Decoder Structure of EXODUS Scheme
3.5 Summary and Observation
For all the bus encoding schemes mentioned above, E(t+1) is obtained from [D(t+1) op E(t)] except the first pattern E(0). The encoder and decoder function must satisfy the following function [5]:
[D(t+1) op E(t)] op E(t) = D(t+1) (3.9)
All the encoding schemes mentioned above aim at reducing transitions in the bus lines. But for some encoding schemes, the data patterns may generate more transitions after encoding than before. For example, assume the original data patterns are from 01010101 to 01010101, in this case there is no transition. In BITS and hihrTS encoding, the encoded patterns are from 01010101 to 00000000, which have four self transitions. In EXODUS encoding, the encoded patterns are from 01010101 to 11001100, which have four self transitions, too. We could easily understand, in this case “Do Nothing” is the best encoding scheme. So in this case BI encoding is better than the other schemes, because the encoded patterns are from 01010101 to 01010101 with no transition after BI encoding. Fig.3.17 shows this example.
E(t)
no transition no transition 4 transitions 4 transitions origin
Fig.3.17 An Example in Which Some Encoding Schemes Make No. of Transitions Become Worse
However, BI is not always the best way. For example, assume the original data patterns are from 01010111 to 00000000, in this case there are five self transitions. In BI encoding, the encoded patterns are from 01010111 to 11111111, which have three self transitions. But in BITS and hihrTS encodings, the encoded patterns are from 01010111 to 01010111, which have no transition. Fig.3.18 shows this example.
E(t)
5 transitions 3 transitions no transition 3 transitions origin
Fig.3.18 An Example in Which BI Encoding is Not The Best Scheme
From above, we know that each scheme has its superiority in specific conditions. If we can analyze this characteristic and gather statistics, we may find a better encoding scheme that has the most improvement on bus transitions.
Chapter 4
The Proposed Bus Encoding Schemes
In this chapter, our encoding schemes are described. Since this thesis focuses on 8-bit wide bus, so is the following discussion. The architectures with the multiple of 8-bit are also suitable for the proposed schemes. For example, if a system uses 16-bit bus to transmit data, we can divide the 16-bit bus into two 8-bit buses for hardware saving. If speed issue is of primary concern, we can use two sets of the proposed encoding architecture.
4.1 Design Overview
We aim to propose dynamic BI-XNOR encoding, which includes three encoding operations - identity, invert and XNOR. As mentioned in the previous chapter, in some conditions “Do Nothing” is better than other complicated encoding schemes. The object of this design is to choose the most suitable encoding operation dynamically for different conditions of data patterns.
4.2 Algorithm of Dynamic BI-XNOR Encoding
4.2.1 Algorithm of Encoding
Let D(t) denote an 8-bits data pattern on a bus at time t, and E(t) is the encoded pattern of D(t). Computing the self transitions between E(t) and its next data pattern D(t+1), if the number of self transitions is less than or equal to 2, the encoding function is:
( 1) ( 1)
E t+ = D t + (4.1) If the number of self transitions is greater than or equal to 6, the encoding function is:
( 1) [ ( 1)]'
E t + = D t + (4.2) If the number of self transitions is equal to 3, 4 or 5, divide the 8-bits bus into two subsets
D (t+1) with each subset consisting of 4-bits. The four MSBs are S D (t+1) and the MS four LSBs are D (t+1) . Compute the number of 1’s in each subset SL D (t+1) . If the S number of 1’s is greater than or equal to the number of 0’s (i.e., the number of 1’s is greater than or equal to 2), the encoding function is:
( 1) ( 1) ( )
S S S
E t + = D t + ☉ E t (4.3) If the number of 1’s is less than the number of 0’s (i.e., the number of 1’s is less than 2), the encoding function is:
( 1) [ ( 1)]' ( )
S S S
E t + = D t + ☉E t (4.4) The encoding flow chart is shown in Fig.4.1.
Fig.4.1 Flow Chart of Dynamic BI-XNOR Encoding Scheme
Assume a series of data patterns D(0), D(1), D(2), …, D(t), D(t+1), …,D(end) are waiting for transmission. The first pattern E(0) is equal to D(0). Then E(1) is obtained from E(0) and D(1) after encoding similarly for all the other E(t). Then we obtain a series of encoded patterns E(0), E(1), E(2), …, E(t), E(t+1), …, E(end).
Fig.4.2 shows an example of dynamic BI-XNOR encoding. Fig.4.2(a) shows data patterns of 8-bit bus to be transmitted. E(0) = D(0) is shown in Fig.4.2(b). Then we compare E(0) and D(1). Since there is only one self transition between them, from
equation (4.1) we get E(1) which is equal to D(1) in Fig.4.2(c). Then we compare E(1) and D(2). Since there seven self transitions between them, from equation (4.2) we invert D(2) to get E(2) in Fig.4.2(d). Next, we compare E(2) and D(3). There are four self transitions between them, so we divide D(3) into two subsets D (3) and MS D (3) . LS Fig.4.2 An Example of Dynamic BI-XNOR Encoding Scheme
which has no self transition. If we adopt XNOR operation on E(t) and D(t+1), E(t+1) will still be 1. Thus the data stream is 1(E(t)) to 1(E(t+1)), and the self transition is still none.
From this we know when the number of 1’s is greater than that of 0’s in D(t+1), XNOR operation is suitable for encoding no matter E(t) is 0 or 1. Next, let us analyze the conditions when D(t+1) is 0. Assume a data stream transits from 1(E(t)) to 0(D(t+1)) which causes a self transition. If we adopt invert and XNOR operations on E(t) and D(t+1), E(t+1) will become 1. Thus the data stream will switch from 1(E(t)) to 1(E(t+1)), such that the self transition is vanished. Assume another data stream is from 0(E(t)) to 0(D(t+1)) which has no self transition. If we adopt invert-XNOR operation on E(t) and D(t+1), E(t+1) will still be 0. Thus the data stream is 0(E(t)) to 0(E(t+1)), and there is still no self transition. From this we know when the number of 1’s is less than that of 0’s in D(t+1), invert-XNOR operation is suitable for encoding no matter E(t) is 0 or 1. Table 4.1 shows the analysis and comparison.
Table 4.1 Analysis and Comparison of XNOR / Invert-XNOR Operations
Encoding E(t) D(t+1) Self Transition E(t) E(t+1) Self Transition
0 1 1 0 0 0
1 1 0 1 1 0
1 0 1 1 1 0
0 0 0 0 0 0
Before Encoding After Encoding
XNOR
Invert-XNOR
Since the total number of 1’s decides the encoding function in the subset, why not use this rule for all data patterns? Assume E(t) is 00011111 and D(t+1) is 00011111 , too.
There is no transition in this condition. If we perform XNOR operation on E(t) and D(t+1), E(t+1) is 11111111. The number of self transitions between E(t) and E(t+1) is three which becomes worse than un-encoded pattern. In this case, no encoding is the best
encoding policy. So we consider the number of self transitions in the original pattern first to dynamically choose appropriate encoding functions. We divide the original pattern into two subsets, because the simulation result show this way has a better performance than just encoding the whole bits of the data.
4.2.2 Algorithm of Decoding
Our encoding scheme simple adopts identity, inverse and XNOR operations, which are easy to decode. Consider E(t+1), if it is obtained from identity operation, D(t+1) is equal to E(t+1). If E(t+1) is obtained from inversion operation, D(t+1) is obtained from the inverse of E(t+1). If the subset E (t+1) is obtained from XNOR operation ( i.e., S
{ ( 1) ( ) }'
Because the first pattern is not encoded, we easily obtain D(0) which is equal to E(0).
Then E(1), E(2), …, E(t), E(t+ 1), …,E(end) are decoded in order and D(1), D(2), …, D(t), D(t+1), …,D(end) are obtained.
4.3 Architecture of Dynamic BI-XNOR Encoding
4.3.1 The Encoder Stage
The encoder structure of dynamic BI-XNOR scheme is shown in Fig.4.3. In this encoding architecture, three control bits C0, C1 and C2 are needed. We divide this architecture into five stages and discuss each stage in detail.
D0(t+1)
In stage 1, D(t+1) and E(t) are compared by the set of XOR gates. If they are identical, there is no self transition between D(t+1) and E(t) and the XOR gate will send 0.
If they are different, there is a self transition and the XOR gate will send 1.
In stage 2, multiplexer 1 calculates the number of self transitions between D(t+1) and E(t) and sends output C0. If the number of self transitions is 0 to 2 or 6 to 8, C0 is set to 0, otherwise C0 is set to 1. Multiplexer 2 calculates the number of self transitions between D(t+1) and E(t) and sends output C1a. If the number of self transitions is 6 to 8, C1a is set to 1, otherwise C1a is set to 0. Multiplexer 3 gathers a statistic for the four MSBs of D(t+1) and sends output C1b. If the number of 1’s is greater than or equal to the number of 0’s (i.e., the number of 1’s is greater than or equal to 2), C1b is set to 0.
Otherwise C1b is set to 1. Multiplexer 4 does the same operations with multiplexer 3 for the four LBSs of D(t+1) and sends output C2. C1b and C2 decides whether D(t+1) should be inverted or not in the set of XOR gates within stage 2.
In stage 3, C1a decides whether D(t+1) should be inverted or not in the set of XOR gates. D(t+1) or [D(t+1)]’ executes XNOR operation with E(t).
In stage 4, the set of 2-to-1 multiplexers controlled by C0 are needed. They select the correct value of E(t+1).
In stage 5, the output E(t) is sent back to the input in the next cycle time. In multiplexer 5, either C1a or C1b is sent as an output C1 because C1a is valid when C0is 0 and C1b is valid when C0is 1.
4.3.2 The Decoder Stage
The decoder structure of dynamic BI-XNOR is shown in Fig.4.4. We divide this architecture into three stages and discuss each stage in detail.
E0(t+1)
In stage 1, E(t+1) execute XNOR operation with E(t) in the set of XNOR gates. C1
indicates whether E(t+1) should be inverted or not in the set of XOR gates.
In stage 2, C1 indicates whether the four MSBs should be inverted or not and C2
indicates whether the four LSBs should be inverted or not in the set of XOR gates. Note that C1 of stage 2 is different from C1 of stage 1. C1 of stage 1 is C1a in the encoder and
indicates whether the four LSBs should be inverted or not in the set of XOR gates. Note that C1 of stage 2 is different from C1 of stage 1. C1 of stage 1 is C1a in the encoder and