Chapter 1 Introduction
1.3 Organization of the Thesis
There are two terms in the denominator which should be maximized to obtain a low subthreshold swing. The first term suggests that a transistor geometry with a high-κ and an ultrathin body could obtain better electrostatic control, and the second term suggests that the swing would be improved if the applied gate field could align with the internal field of the tunnel junction.
Therefore, we use propose the nanowire TFET with raised source/drain, whose process can fabricate silicon nanowires and raised source/drain simultaneously without the use of advanced lithography tools [18], for the first time. With the nanowire structure with the superior gate electrostatic control and the raised source/drain which could reduce the resistance, we hope to achieve the desirable TFET performance, such as the steep subthreshold swing and the high on/off current ratio.
1.3 Organization of the Thesis
There are four chapters in this thesis. Chapter 1 depicts the background of the use of the polysilicon and the evolution of the multi-gate technique from planar device to gate all around nanowire. It also briefly describes advantages and the current situation of the tunnel field-effect transistor.
In chapter 2, we describe the operation principle of TFET and then present the process of the poly-Si nanowire tunnel TFTs with raised source/drain with different gate conditions: underlap or
6
overlap. Besides, the measurement tools and methods are also introduced and defined in this chapter.
In chapter 3, the device characteristics and measurement results are analyzed and discussed in detail, such as, the on/off current and subthreshold swing in relation to the length and numbers of nanowires. In order to confirm the tunneling mechanism of our devices, the activation was extracted. And the plasma treatment was done and discussed.
In chapter 4, the conclusion of this study is presented. Finally, the future work and the suggestion of device improvement are presented.
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Figure 1-1 Moore’s Law [4]
Figure 1-2 The different types of the gate electrode wrapping the channel [7]
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Figure 1-3 The evolution of the transistor generation introduced by Intel
Figure 1-4 Transfer characteristics of a MOSFET shows that IOFF increases exponentially because of the invariant subthreshold swing, S = 60 mV/dec. [9]
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Figure 1-5 The n-channel conventional MOSFET and the n-channel TFET. The left side is in the off state and the right side is in the on state. [19]
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Chapter 2
Device Fabrication and Experimental Setup
2.1 The Principle of Tunnel Field-Effect Transistors
The Tunnel Field-Effect Transistor consists of a gated p-i-n diode which is reverse biased to get an ultra-low leakage current. Figure 2-1a shows a typical planar p-type TFETs, which has an n+ source, a p+ drain and the intrinsic substrate. Figure 2-1b shows the energy band diagram of operation of a p-type TFET including the off state (dashed blue lines) and the on state (red lines).
In the off state, the valence band edge of the channel is below the conduction band edge of the source, so there is no current flowing through the channel due to no empty states allowing holes tunneling into the channel which is the reason that the off current is quite low. In the on state, the energy band of the channel is pulled up, the valence band edge of the channel is higher than the conduction band edge of the source, so holes can tunnel from the source to the channel.
Only carriers in energy window, ΔΦ (green shading), can tunnel into the channel, because the high and low energy part of the source Fermi distribution are cut off, as illustrated in Figure 2-1b, which is like the conventional MOSFET that is cooled down to a low temperature.
Therefore, the subthreshold swing, S, could be below 60 mV/dec, as shown in Figure 2-1c.
However, the channel valence band would be lifted up by the gate voltage, and the tunneling length would be reduced by the gate voltage simultaneously, so the subthreshold swing of a TFET is not a constant (Figure 2-1c).
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2.2 Experimental Procedure
The process flow of the poly-Si thin-film tunnel field-effect transistors is shown in Figure 2-2 (a)-(j). First, we utilized a 6 inch (100) silicon wafer as a substrate and deposited wet oxidation.
The dummy sandwich structure Si3N4 (30 nm) / SiO2 (20 nm) / Si3N4 (30 nm) was deposited by low-pressure chemical vapor deposition (LPCVD). After the patterning and etching of the nanowire definition, the cavities of the oxide layer is etched laterally by the selective wet etching.
The 100 nm amorphous Si (α-Si) layer was then deposited by LPCVD, which formed the Si nanowire channel and the raised S/D at the same time. The raised source region was implanted with BF2+, at 40 keV, at 5 x 1015 cm-2 and the drain was implanted with P+, at 26 keV, at 5 x 1015 cm-2, then the α-Si layer was crystallized by solid-phase crystallization (SPC) at 600oC for 24 h in N2
ambient. Then the raised source/drain and the nanowire region were patterned and dry etched. The dummy sandwich structure was removed by wet etching by using H3PO4 and diluted HF, and Si nanowires were suspended. Next, 7 nm oxide as the gate dielectric and 250 nm in-situ n+ polysilicon as the gate electrode was deposited. Finally, we completed the fabrication after the lithography and the dry etching. The poly-Si gate was designed in two conditions: underlap gate and overlap gate shown in Figure 2-2 (j) and (k).
The underlap gate devices had additional processes to improve the device performance. After underlap gate devices was deposited TEOS oxide of 30 nm as the liner oxide, the source and drain was implanted and then annealed by microwave with 300 W for 600 sec.
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2.3 Method of Device Parameter Extraction
2.3.1 Measurement Tool Setup
The measurement tool setup for the I-V characteristics of nanowire TFETs are presented in Figure 2-3, including the SCS Parameter Analyzer (Keithley 4200), the pulse pattern generator (Agilent 81110A), the low leakage current switch mainframe (Keithley 708A) and the probe station.
Keithley 4200 is equipped with programmable source-monitor units (SMU) and provides a high resolution to measure DC I-V and pulse characterization of semiconductor devices.
Agilent 81110A with two pulse channels supplies high timing resolution pulse. When a device is measured in the probe station, KEITHLEY 708A, which is configured a 10-input × 12-output switching matrix, switches the signal from KEITHLEY 4200 and Agilent 81110A.
2.3.2 Threshold Voltage
There are two physical definitions for the threshold voltage of a TFET: gate threshold voltage and drain threshold voltage, which are based on the saturation of the tunneling barrier length shortening with respect to VG and VD [20]. These two values can be extracted by (trans)conductance derivative. In this thesis, we will use the constant current method and the onset voltage to extract the threshold voltage. The constant current is defined as the gate voltage that yields a drain current of 10 nA which is widely used in industry because of its simplicity [21]
and also utilized in most of the studies of TFTs. The onset voltage is defined as the gate voltage when the tunneling behavior begins which is also used in tunnel FETs [22].
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2.3.3 Subthreshold Swing
The subthreshold swing (S.S.) is a widely used value to judge the gate controllability of a transistor. The typical transfer characteristics of a MOSFET, which is ID-VG curve, includes three regions: the subthreshold region, the linear region and the saturation. The subthreshold swing is defined as the inverse slope of the drain current (ID) over the gate voltage (VG) in the subthreshold region:
𝑆. 𝑆. = [𝑑𝑙𝑜𝑔𝐼𝐷 𝑑𝑉𝐺 ]
−1
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Figure 2-1 Principle of operation of a TFET. (a) Typical structure of planar p-type TFET (b) Schematic energy band profile for the off state and the on state in a p-type TFET (c) The ID-VG characteristics of a TFET compare with the limit of 60 mV/dec [9].
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Wet Oxide Si
3N
4TEOS Si
3N
4(a) wet oxide (500 nm) and Si3N4 (30 nm) / TEOS (20 nm) / Si3N4 (30 nm)
Wet Oxide Si
3N
4TEOS Si
3N
4(b) nanowire region definition by lithography and dry etching
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Wet Oxide Si
3N
4TEOS
Si
3N
4(c) cavities etching by HF wet selective etching
Wet Oxide Si
3N
4TEOS
Si
3N
4α-Si
(d) amorphous Si (α-Si) (100 nm) deposition by LPCVD
17 p-type implant
Wet Oxide Si
3N
4TEOS Si
3N
4α-Si
(e) p-type implantation
n-type implant
Wet Oxide Si
3N
4TEOS Si
3N
4α-Si
(f) n-type implantation
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Raised S/D
(g) nanowire region and raised S/D by dry etching
Raised S/D
Wet Oxide Si3N4 TEOS
Si3N4
Poly-Si nanowire
(h) solid phase crystallization (SPC) 600oC 24 hr
Wet Oxide Si
3N
4TEOS Si
3N
4α-Si nanowire
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Poly-Si nanowire
Si3N4
Wet Oxide Poly-Si nanowire
(i) nanowire channels revealed by H3PO4 wet etching
Underlap n-type Poly-Si
Gate
Poly-Si
Si3N4
Wet Oxide Poly-Si nanowire
(j) underlap gate: gate dielectric and in-situ n-gate deposition, and dry etching
20 Overlap
n-type Poly-Si Gate
Poly-Si
Si3N4
Wet Oxide Poly-Si nanowire
(k) overlap gate: gate dielectric and in-situ n-gate deposition, and dry etching
Figure 2-2 (a)-(k) The process flow of the poly-Si nanowire thin-film TFET with raised source/drain
Figure 2-3 The experimental setup for the transfer characteristics of the poly-Si nanowire thin-film TFET with raised source/drain
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Chapter 3
Poly-Si Nanowire Tunnel Thin-Film Transistors
3.1 Introduction
In this chapter, we will discuss the characteristics of the poly-Si thin-film transistors with underlap gate and overlap gate, respectively. With different conditions such as, length, numbers of nanowires and different diameter, the on/off current ratio, the subthreshold swing and the threshold voltage will be demonstrated.
3.2 Characteristics of Poly-Si Nanowire Tunnel Thin-Film Transistors with Underlap Gate
Figure 3-1 is the cross-sectional TEM image of a nanowire channel. The dummy sandwich NON stack was soaked in diluted HF to obtain a cavity of 20 nm height and of 25 nm / 35 nm / 45 nm depth. The diameter of NWs would be further reduced after the dry etching (Figure 2-2 (h)) and the H3PO4 wet etching (Figure 2-2 (i)). The final shape of a NW is elliptic cylindrical.
The ID-VG characteristics of a poly-Si nanowire tunnel TFT with underlap gate is shown in Figure 3-2. The behavior performs low ON current (ION ~ 8x10-12 A) and poor subthreshold swing (S > 1000 mV/dec). The low ON current can be attributed to large parasitic resistance and low doping concentration at source region. The S.S. degradation is due to the low doping concentration and the trap assisted tunneling (TAT). The low doping concentration makes the tunneling field lower and thus the tunneling distance is larger which results in poor S.S. Because
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of additional implantation of underlap gate devices, there are traps appearing in the tunneling junction which enhances the TAT.
The on resistance of a poly-Si nanowire tunnel TFT with underlap gate is up to 50 MΩ as shown in Figure 3-3 (a), which confirms the very large resistance. Therefore, in order to improve the current drive of an underlap NW TFET, an overlap NW TFET was proposed. With a gate-to-source/drain-pad overlap structure, the on resistance could be successfully reduced from 50 MΩ to 150 kΩ as shown in Figure 3-3.
3.3 Characteristics of Poly-Si Nanowire Tunnel Thin-Film Transistors with Overlap Gate
The ID-VG characteristics of a poly-Si NW tunnel TFT with overlap gate in n-type and p-type are shown in Figure 3-5 (a) and (b). The curves exhibit higher ON current and better S.S which benefit from the overlap structure. However, the S.S. is still unacceptably large due to an occurrence of TAT and a less steep source-channel doping profile owing to long term annealing.
We will discuss the TAT by using the temperature measurement and extracted activation energy later.
The source-gate-channel doping profile can be seen in Figure 3-6 (b) which is the cross-section image of the source pad in the simulation. Due to long term annealing, phosphorous diffused from the drain pad into nanowires and source pad as shown in Figure 3-7, and BF2 was not implanted deep avoiding damage nanowires, there is an n- region between the source and nanowires. When an n-type TFET is on (the applied gate voltage is positive), the distance between the inversed nanowire channel and p+ region is so long that the tunneling length is large
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as illustrated in Figure 3-8.
Figure 3-9 presents the on and off current versus the gate length of poly-Si nanowire TFET with diameter ~ 12 nm. The drive current and off-leakage current for single crystal are nearly independent of the gate length [23]. The invariant drive current is also found in tunnel TFTs because tunneling current dominates at on-state. On the other hand, the off current gets higher as the gate length is shorter due to the larger diffusion coefficient of phosphorus. When the gate length is short, phosphorus distribution would be near the p+ source region, and it leads more current of the Schottky-Read-Hall (SRH) recombination. Thus, the leakage current is larger.
The threshold voltage by constant current versus gate length of n-type and p-type devices is presented in Figure 3-10. With the excellent gate control of nanowire structure, the threshold voltage roll-off is not seen, which means the immunity of SCE is good. The shift of the threshold voltage at different drain voltages is observed due to the trapped charges at gate dielectrics.
Figure 3-11 illustrates the dual sweep ID-VG curve for n-type device. For n-type device, the reverse sweep shifts toward the left, that is, gate dielectrics would trap holes because of gate injection. Figure 3-12 shows the threshold voltage by onset voltage versus gate length of n-type and p-type devices. The onset voltage is defined as the gate voltage that charges start tunneling into channel. The onset voltages at larger drain voltage are higher than ones at lower drain voltage which is different from the trend illustrated in Figure 3-10, because the onset voltage is defined at the lowest drain current that strongly depends on the leakage current. When the drain voltage is larger, the bias of tunnel junction is larger, too, and thus reverse tunneling occurs easier.
Figure 3-13 illustrates the subthreshold swing as a function of the gate length of n-type and p-type devices. Because of the tunneling junction located in the sidewall of nanowires in the
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source pad, the subthreshold swing is independent of the gate length.
Figure 3-14 shows the dependence of pairs of nanowires and the drain current for (a) n-type and (b) p-type. With number of nanowires increases, the effective width of channel increases. It is important to note that the SRH recombination current rises, too. As a consequence, the on and off current both increases.
Figure 3-15 illustrates the drain current versus the nanowire diameter for (a) n-type and (b) p-type. The on current is independent of the nanowire diameter because the tunneling junction is mainly at the sidewall of nanowires, and in this case, the oxide thickness of NON stack is all the same even in different diameter conditions.
The mechanism of tunnel FETs is illustrated in Figure 3-16. The first one is band-to-band tunneling, BTBT. The second one is trap assisted tunneling, TAT. The third one is field emission from traps which is also classified as TAT. Electrons from the valence band in the p+ source region might tunnel through the bandgap into traps and then tunnel or thermally emit out of traps into the conduction band of n+ region. In order to confirm operation of devices, the I-V measurement was carried out with various temperature and the extracted Arrhenius plot is shown in Figure 3-17. By using values of ln (ID) at different gate voltage and different temperature, the slope was calculated which is known as the activation energy. The corresponding activation energy as a function of gate voltage is presented in Figure 3-18. At the off state (VG ~ 0.5 V), the activation energy is about 0.5 eV, around half of the band gap of silicon, which means the SRH recombination dominates [24]. With the increase of the gate voltage, the activation energy decreases and is still larger than 0.1 eV until 3V which means that TAT occurs [25]. Because band-to-band tunneling (BTBT) shows weak dependence on temperature, an activation energy of BTBT should be below 0.1 eV. Therefore, poly-Si nanowire tunnel TFTs are mainly operated by
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TAT.
In an effort to reduce traps that would cause TAT, overlap gate devices were done with the NH3 plasma treatment. The on/off current and S.S. as a function of the plasma treatment time is shown in Figure 3-19 and 3-20. When the plasma treatment time is from 0 min to 3 min, the on/off current and S.S. all reduced due to the elimination of traps which also reduce the both TAT and SRH recombination. However, as the plasma treatment time is up to 5 min, the off current and S.S. all increased because overlong treatment time would lead to damage in devices. The degradation of the off current and S.S. are observed.
3-3 Summary
We demonstrated the poly-Si nanowire tunnel TFTs for the first time. Poly-Si nanowire tunnel TFTs with underlap gate performed high subthreshold swing and low on/off current ratio.
Thus, we proposed overlap gate structure, but the characteristics is still poor. By the TCAD simulation of the doping profile, we found that phosphorus would diffuse into nanowires and even p+ pad. The gate could not control the tunneling junction leading to low tunneling efficiency.
Thus, the drive current and subthreshold swing are degraded. Temperature-dependent I-V measurements and the extracted activation energy show that the tunneling current is mainly due to trap assisted tunneling rather than band-to-band tunneling, which is also the cause of poor performance. In addition, some overlap gate devices were exposed to NH3 plasma. Consequently, traps would be eliminated in short plasma treatment time (~ 3 min), but nanowires would be damaged in overlong plasma treatment time (> 5 min) that degrade the performance.
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Figure 3-1 Cross-sectional transmission electron microscope (TEM) images of the poly-Si nanowire thin-film TFET
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Figure 3-2 The ID-VG characteristics of the poly-Si nanowire thin-film TFET with Underlap gate
-1 0 1 2 3 4
10
-1410
-1210
-10Underlap n-NWTFET D
NW~ 12 nm
L
G= 3 m
Dra in Current (A)
Gate Voltage (V)
V
D= 1 V
V
D= 2 V
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(a)
(b)
Figure 3-3 The on resistance of the poly-Si nanowire thin-film TFET (a) with underlap gate (b) overlap gate
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30
(a)
(b)
Figure 3-6 The dopant concentration simulation of a poly-Si nanowire thin-film TFET (a) the cross-sectional image of source-gate-drain (b) the dashed line cross-sectional image of (a)
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Figure 3-7 The top view of the dopant concentration simulation of a poly-Si nanowire thin-film TFET
Figure 3-8 The energy band diagram of the dashed line in Figure 3-6(b)
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(a)
(b)
Figure 3-9 The on/off current as a function of the gate length with DNW ~ 12 nm for poly-Si nanowire tunnel TFTs (a) n-type (b) p-type
0 1 2 3
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Figure 3-10 The threshold voltage (constant current) as a function of the gate length for poly-Si nanowire tunnel TFTs with DNW ~ 12 nm (a) n-type (b) p-type
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0 2 4
10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6
Drain Current ( A)
Gate Voltage (V)
VD = 1 V n-NWTFET DNW ~ 12 nm LG = 0.5 m
Figure 3-11 The dual sweep ID-VG curve of the n-type poly-Si nanowire tunnel TFT with DNW ~ 12 nm and LG = 0.5 μm at VD = 1V
35
36 poly-Si nanowire tunnel TFTs (a) n-type (b) p-type
0 1 2 3
37 for poly-Si nanowire tunnel TFTs (a) n-type (b) p-type
38
(a)
(b)
Figure 3-15 The drain current as a function of the pairs of NW Diameter with LG = 1 μm for poly-Si nanowire tunnel TFTs (a) n-type (b) p-type
10 20 30
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Figure 3-16 The mechanisms of tunneling current: 1: band-to-band tunneling, BTBT 2:
trap assisted tunneling, TAT 3: field emission from traps
Figure 3-17 The Arrhenius plot at VG = 0.6 V, 1.5 V and 2.5 V for n-type poly-Si nanowire tunnel TFTs
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Figure 3-18 The corresponding activation energy versus gate voltage
Figure 3-19 The on and off current error bar versus plasma treatment time for poly-Si nanowire tunnel TFTs
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Figure 3-20 The subthreshold swing versus plasma treatment time for poly-Si nanowire tunnel TFTs
0 3 5
300 400 500 600 700
n-NWTFET D
NW~ 12 nm L
G= 1 m
Plasma Treatment Time (min)
Subth res hol d Sw ing (m V/de c)
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Chapter 4
Conclusions and Future Work
4.1 Conclusions
In this study, we demonstrate poly-Si nanowire tunnel TFTs with raised source/drain which was fabricated by dummy NON stack without using advanced lithography tools. Underlap gate devices have bad performance, such as, high subthreshold swing, low on current and low on/off current ratio. Thus, Overlap gate devices were fabricated and exhibit better subthreshold swing and on/off current ratio, but the result are still below our prediction. Even though the immunity of SCE is good which is observed from the invariance of threshold voltage and subthreshold swing with different gate length.
By the TCAD simulation of the doping profile, we found that phosphorus would diffuse into nanowires and even p+ pad. BF2 didn’t distribute well in the raised structure and was even far from nanowires. Poor doping profile and the gate which could not control the tunneling junction lead to large on resistance and tunneling distance which also degrades the behavior of TFETs.
By the TCAD simulation of the doping profile, we found that phosphorus would diffuse into nanowires and even p+ pad. BF2 didn’t distribute well in the raised structure and was even far from nanowires. Poor doping profile and the gate which could not control the tunneling junction lead to large on resistance and tunneling distance which also degrades the behavior of TFETs.