Organization of the thesis - 利用尖角效應提高寫入電場於薄膜電晶體之記憶體元件應用

In Chapter 1, an introduction about the general background of non-volatile

memory (ex: floating gate memory, SONOS-type memory and SONOS-type TFT memory) devices are described. SONOS-type TFT memory has got many attentions since system on panel (SOP) is very popular. According to the low power consumption, high program/ erase speed and excellent reliability issues, many novel structures and methods has been proposed. In chapter 2, we will demonstrate the process flow of TFT-SONOS devices and experimental measurement setup which shows schemes for programming/ erasing operation. The TEM cross-section would show to prove corners at each side of channel width direction was made. We will discuss the electric performance for different width dimension, and the devices reliability at different temperatures would also be talk here in chapter 3. In chapter 4, the same structure would make and we follow the EOT scaling down issue, the device performance and reliability both be discuss. Last, the conclusion and future work will be present in chapter 5.

Table 1.1 The non-volatile memory technology requirements for NAND Flash memory in ITRS 2010 [1.5]

Table 1.2 The non-volatile memory technology requirements for NAND Flash memory in ITRS 2010 [1.5]

Fig. 1.1 Potential applications of NAND Flash memory comparing projected cost reductions with Flash capacitor by technology.[1.2]

Fig. 1.2 The schematic of the conventional floating gate non-volatile memory devices.

Fig. 1.3 The Id-Vg curves for the different program state “1” and erase state “0” ; showing the Vt shift and memory window.

Fig. 1.4 Schematic of the electron loss by Frenkel-Poole mechanism (a) a single point defect in thin tunneling oxide may induce Frenkel-Poole tunneling (b) a single point defect in thick tunneling oxide is insufficient to cause Frenkel-Poole tunneling.

Fig. 1.5 Schematic of the total electron will be leaked through tunneling oxide by Frenkel-Pool mechanism due to floating gate is conductive.

Fig. 1.6 Schematic of the conventional SONOS-type non-volatile memory devices.

Fig. 1.7 The SONOS NVM devices were programmed by FN tunneling mechanism.

Fig. 1.8 The SONOS NVM devices were programmed by Channel Hot Carrier mechanism.

Fig. 1.9 The SONOS NVM devices were erased by FN tunneling mechanism.

Fig. 1.10 The SONOS NVM devices were erased by BTBHH mechanism.

Fig. 1.11 The energy band diagram of the SONOS NVM device during erasing by BTBHH mechanism.

Fig. 1.12 The SONOS NVM devices were erased by STHH mechanism.

Chapter 2 Device Fabrication and Experimental Setup 2.1 Introduction

Since the traditional floating gate is replaced by the charge trapping layer [2.1], the tunneling oxide thickness can be scaled down to 3nm. Therefore, the programming and erasing speed is about the microsecond and millisecond range which is enhanced. Many studies point out the charge retention time would be related to the oxide thickness. As the oxide thickness decreased, the probability of charges detrapped by trap – assist – tunneling is multiplication [2.2]-[2.5]. In order to maintain the retention time over ten years, the oxide thickness is recovered to 4~5 nm to achieve the requirement of devices reliability. In this chapter, we will introduce a new structure to optimize TFT-SONOS memory with M-shape channel and this structure improves P/E speed through a low cost process. This TFT-SONOS memory with lower V_t, faster programming speed and longer retention can be obtained, highly promising for realization of 3D circuit integration. The performance and reliability of devices, including data retention, P/E cycling test, and gate/ drain disturbance were investigated.

2.2 Experimental Procedure

A 6-in (100) bulk silicon wafer was used as the base material substrate. First, a 500-nm thermal oxide layer was grown on the Si-substrate to form a glass substrate. A 150-nm amorphous silicon (α-Si) layer was then deposited using low-pressure chemical vapor deposition (LPCVD). The deposited α-Si layer was recrystallized by solid-phase crystallization (SPC) at 600°C and annealed for 24 hr in N2 ambient.

Then, 35-nm wet oxide and 150-nm LPCVD nitride films were deposited on the wafers. Active regions were patterned by lithography and a dry etching process, as Fig.

2.1 (a) shows. Wafers were wet oxidized to obtain 140-nm wet oxide, forming a bird beak at the channel-width direction. This is similar to local oxidation of silicon (LOCOS) isolation in a MOSFET process, as Fig. 2.1 (b) shown. Using the 140-nm wet oxide as a hard mask to define TFT - island two corners were added to each side of the channel width direction as Fig. 2.1 (c) shows. The control samples excluded this LOCOS-step. All wafers underwent a BOE-dip to remove oxidation and simultaneously create an undercut under the poly-Si, creating two additional corners in the width direction, as Fig. 2.1 (d) shows. A 47-nm oxide-nitride-oxide (ONO) multilayer gate dielectric was deposited by LPCVD, including a 15-nm tunneling oxide, 12-nm nitride trapping layer, and 20-nm blocking oxide. A 200-nm undoped poly-Si layer was then deposited, and a gate defined by lithography. Fig. 2.1 (e) shows the control sample without an M-shape channel for comparison. The source, drain, and gate were then doped with self-aligned implantation of phosphorous. A 550-nm oxide passivation layer was deposited and contact holes were patterned. Finally, Al metallization was performed.

As shown in Fig. 2.2, we could assume our structure is composed by three transistors, like A-A’, B-B’ and C-C’. The A-A’ and C-C’ are the part of source and drain. Both of them also have additional corners at channel-width direction. The B-B’

has oxide-nitride-oxide and poly-si gate and it also shows it has addition corners at channel-width direction. From Fig. 2.2, it helps us to understand our structure well through channel-width direction.

2.3 Measurement and Equipment Setup

The experimental setup for the I-V and threshold voltage characteristics measurement of this TFT-SONOS device is illustrated in Fig. As shown in Fig. 2.3, the main electrical characteristics measurement and control system here are Keithley 4200 which equipped with programmable source-monitor units (SMU) and a high resolution current amplifier with pico-ampere range to facilitate the device current measurement. The Agilent 81110A with two pulse channel could provide the high timing resolution for transient pulse level and P/E cycling endurance test for flash memory device. It’s the main equipment to afford the programming and erasing pulse.

For this reason, in order to precisely control the pulse level and pulse timing of Agilent 81110A memory device. It’s the main equipment to afford the programming and erasing pulse. In addition, the C++ language is used to control different measurement instruments, such as the low leakage current machine Keithley 708A with 10-input and 12-output switching matrix switches the signals automatically to the device under test (DUT) immediately, the device reliability after P/E cycling stress and gate disturbance…etc.

2.4 Operation of Program/ Erase Mode

Memory devices are operated by variety principles, and major program mechanisms are Fowler-Nordheim (F-N) Injection [2.6]-[2.8] and channel-hot-electron (CHE) injection [2.9]-[2.11]. The programming mechanism of channel-hot-electron (CHE) injection requires high positive voltage connected to the gate and drain terminals. While the programming scheme switches on, as described as we mention before, the carriers are accelerated by high lateral electrical field that will produce the large amount of impact ionization. The lots of electron-hole pairs would redirect due to the high vertical electrical field in the neutral gap region which

increases the probability of electrons injection into nitride trapping layer. The electron injection efficiency is lower and the high energy electrons would damage the tunneling oxide. Due to those reasons, we choose the programming mechanism of Fowler-Nordheim (F-N) injection as shown in Fig. 2.4. Only positive voltages connected to the gate terminal and Source/ Drain/ Well terminals are grounded. The voltage drop makes the electric field of tunneling oxide is more than 6 MV/cm, and electrons would be injected from channel into trapping layer owing to the electric field applied to tunneling oxide. The erase operation uses the substrate transient hot-hole (STHH) injection mechanism [2-12]. Fig. 2.5 shows the erase characteristic with negative bias connected to the gate terminal and huge positive bias connected to source/ drain terminals, where a huge reverse bias is added to the PN junction to cause the PN junction in breakdown. An avalanche breakdown in PN junction caused a lot of electron-hole pairs, and only added a small gate bias (V_g > 0V) a large number of holes will be attracted then injected into nitride layer to erase electrons.

2.5 Disturb Characteristics

Fig. 2.6 shows the possible disturbances phenomenon of equivalent circuit schematic in NAND architecture. In general, there are including program disturbance and read disturbance [2-13][2-14]. The disturbed phenomenon of programming process happened to the common word-line (WL) device in memory array is named gate disturbance. This is because the adjacent memory cells used the same word-line result in the electrical stress on the unselected cell. It may make slightly electrons tunneling into the trapping layer which to cause threshold voltage fluctuations. The serious program disturbance means that the unselected memory cell became high state from low state during the long time stress. Another program disturbance condition is

that electrons in nitride trapping layer may detrap by Frenkel-Poole emission and then tunneling to control gate through the blocking oxide by defects while applying the large positive bias at gate terminal. Such the excess leakage current will degrade the device reliability, too.

The second phenomenon is the read disturbance. Especially in NAND array, while the selected cell is reading, all of the memory cell in the string must be turned on to form the channel conduction. As a result, the unselected memory cell in NAND string will be stressed by the high pass voltage in reading mode. It will lead the electrons injecting into storage layer results in non-ideal effect of threshold voltage increase, called read disturbance. In addition, in the NAND architecture, the unselected memory cells act like the serial resistance in the circuit brings read current degradation. For this reason, the read speed in NAND architecture is slower than the NOR architecture and can’t read random access.

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Fig. 2.1 (a) (b) (c) (d) Schematic view of an experimental process for fabricating an M-shape channel. (e) Schematic view for the control sample.

Fig. 2.2Schematic view of this structure from channel-length direction. It is clearly shown the additional corners at channel-width direction.

Fig. 2.3 The experimental setup of the I-V and threshold voltage characteristics measurement of the memory device.

Fig. 2.4 The schematic mechanism of the FN tunneling for SONOS NVM devices programming.

Fig. 2.5 The schematic mechanism of the substrate transient hot-hole (STHH) injection for SONOS NVM devices erasing.

Fig. 2.6 The equivalent circuits schematic of the memory cell. During Cell A is programmed, the gate disturbance takes place in Cell B and the drain disturbance takes place in Cell C.

Chapter 3 Corner Effect of TFT-SONOS Memory Devices

3.1 Introduction

The most important demand of memory device is the performances of program/erase speed. We all hope the program/erase speed could as faster as possible.

In addition, the cost per bit must be reduced in order for Flash technology to access the profitable market of mass storage for portable applications. The electric field enhancement is a good way to improve the program/erase speed and the efficiency was be proofed by many literatures [3-1][3-2]. In this chapter, we will introduce the experimental device of the Electric field enhancement memory cell with different corner number in NAND string. The program/erase speed and reliability issue would be discussed here. The programmed and erased of each sample were used Fowler-Nordheim (F-N) Injection and Substrate transient hot-hole (STHH) injection.

3.2 Results and Discussions

The structures of TFT-SONOS memory is as shown in Fig. 3.1 and Fig. 3.2. Fig.

31 is the TEM image of control sample and it could clearly show there are no adding corners at the channel width direction. As shown in Fig 3.2, channel film is look like

“M” through the cross-section view of width direction. We called this structure is

“M-shape” TFT-SONOS memory. And we also reinforce the topic of increasing number of corners, there were additive corners form undercut.

Fig 3.3 shows the program speed characteristics of the control sample and M-shape sample at Width/Length = 10um/ 10um, and the program voltages were at 35 V. The programming method is Fowler-Nordheim (FN) tunneling because the

voltage drop make the electric field of tunneling oxide is more than 6MV/cm. Using FN programming, a memory device without corners at the each side of channel shows a slow programming speed at a gate voltage (V_G) of 35 V comparable to the literatures [3-2][3-3]. On the other hand, M-shape sample (a memory device with corners) the programming V_thwindow of 7.06 V is obtained at V_G=35 V for 100-ms.

Fig 3.4 shows the program speed characteristics of the control sample and M-shape M-shape sample at Width/ Length = 5um/ 10um, and the program voltages were at 35 V. M-shape sample (a memory device with corners) the programming Vth window of 9.25 V is obtained at VG=35 V for 100-ms.

From Fig 3.3 – 6, it is clearly shown that the programming speed is increased by local electric field enhancement. The electric field at corner region near the SiO2/poly-Si interface is much higher and the local enhancement of electric field can be achieved [3.4]. A higher electric field increases the likelihood of FN tunneling, allowing devices with corners to achieve a high program speed. Although the M-shape structures had locally field enhancement, it hadn’t shown any double hump in Id-Vg characteristics as shown in Fig 3.11. It is because it had rounded corners.

Rounded corner is not only reduced electric force lines crowding but also made induced free carriers more uniform [3.5].

Fig 3.7 shows the erase speed characteristics of the control sample and M-shape sample at Width/ Length = 10um/ 10um, and the erase voltages were at VG= -7 V and V_S=V_D=18 V. The erasing method is substrate transient hot-hole (STHH) injection where a huge reverse bias is added to the PN junction to cause the PN junction in breakdown. An avalanche breakdown in PN junction caused a lot of electron-hole pairs, and only added a small VG of -7 V a large number of holes will be attracted then injected into nitride layer to erase electrons. On the other hand, M-shape sample (a memory device with corners) the erasing Vth window of 1.34 V is obtained at VG= -7 V and V_S=V_D=18 V for 100-ms [3.6]. Fig 3.8 shows the program speed characteristics of the control sample and M-shape sample at Width/ Length = 5um/

10um, and the program voltages were at V_G= -7 V and V_S=V_D=18 V. M-shape sample (a memory device with corners) the programming Vth window of 2.39 V is obtained at V_G= -7 V and V_S=V_D=18 V for 100-ms. Fig 3.9 shows the program speed characteristics of the control sample and M-shape sample at Width/ Length = 2um/

10um, and the program voltages were at V_G= -7 V and V_S=V_D=18 V. M-shape sample (a memory device with corners) the programming Vth window of 3.3 V is obtained at at V_G= -7 V and V_S=V_D=18 V for 100-ms. Fig 3.10 shows the program speed characteristics of the control sample and M-shape sample at Width/Length = 1um/

10um, and the program voltages were at V_G= -7 V and V_S=V_D=18 V. M-shape sample (a memory device with corners) the programming Vth window of 3.5 V is obtained at at V_G= -7 V and V_S=V_D=18 V for 100-ms.

From Fig 3.7 – 10, the programming efficiency is much higher than the erasing efficiency. This is because holes encounter a much higher barrier height (4.6eV) than electrons [3.6]. Although the erasing efficiency is not very well, as the width scaling

the erasing efficiency is improved.

From Fig 3.3 – 6 and Fig 3.7 – 10, we could find program window and erase window increase as channel width scaled down. There was an inverse proportion relationship between memory window and width as shown in Fig 3.12. As the channel width decreased, the Vth window of programming at a width of 1μm of M-shape TFT-SONOS increased by approximately 20% compared to the control sample. This kind of improvement also shows on erase window. In Fig 3.13, the Vth window of erasing at a width of 1μm of M-shape TFT-SONOS increased by approximately 57%

compared to the control sample. Nevertheless, it still illustrates the retention performance of the M-shape TFT-SONOS memory at different temperatures.

M-shape TFT-SONOS memory still has excellent reliability even at high-temperature of 100 °C, resulting in a 5% data loss for 104-sec as shown in Fig 3.14. Results show that the addition of corners at each side of the channel in the width direction has no effect on data loss, even in short-width devices. Fig 3.15 shows the temperature activation energy (Ea) for the projection of retention lifetime. The data retention of the M-shape TFT-SONOS memory is well above ten years at 73 °C, with an Ea of 1.604 eV [3.7].

3.3 Summary

This study demonstrates structure-shape TFT-SONOS memory with sharp corners.

This M-shape TFT-SONOS memory design improves the program/erase speed and program/erase window in contrast to the control sample. The enhanced electrical field in the corner regions generates a higher program current under FN programming.

However, this corner effect does not decrease retention at room temperature. M-shape TFT-SONOS memory still has remarkable retention at different widths and high

temperature baking. The proposed M-shape TFT-SONOS memory significantly improves the memory window and achieves excellent retention. Thus, the proposed M-shape TFT-SONOS memory seems promising for future SOP designs.

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Fig. 3.1(a) The TEM images of control samples through width direction.

There are no addition corners on each side of channel width direction (b) It is the enlarge drawing of corner.

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Fig. 3.2(a) The TEM images of M-shape samples through width direction.

There are addition corners on each side of channel width direction (b) It is the enlarge drawing of corner.

Fig 3.3 Program characteristic of M-shape TFT-SONOS memory. The program speed and memory window in TFT-SONOS memory increased faster than those in the control sample at Width=10μm.

faster than those in the control sample at Width=5μm.

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Fig 3.5 Program characteristic of M-shape TFT-SONOS memory. The program speed and memory window in TFT-SONOS memory increased faster than those in the control sample at Width=2μm.

Fig 3.6 Program characteristic of M-shape TFT-SONOS memory. The program speed and memory window in TFT-SONOS memory increased faster than those in the control sample at Width=1μm.

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Fig 3.7 Erase characteristic of M-shape TFT-SONOS memory. The program speed and memory window in TFT-SONOS memory increased faster than those in the control sample at Width=1μm

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35 faster than those in the control sample at Width=2μm.

Fig 3.10 Erase characteristic of M-shape TFT-SONOS memory. The program speed and memory window in TFT-SONOS memory increased faster than those in the control sample at Width=1μm.

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Fig. 3.11 The “ double hump” was not shown here for ID-VG curves. The rounding corners help us solve the problem of hump.

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Fig. 3.12 M-shape TFT-SONOS memory has width dependence. Program windows increased significantly as the width decreased.

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Width (um)

W/O corners Corners Erase @ VG = -7V VD = VS = 18V

Fig. 3.13 M-shape TFT-SONOS memory has width dependence. Erase windows increased significantly as the width decreased.

Fig. 3.14 Retention characteristics of M-shape TFT-SONOS memory window at different temperature 25℃, 75℃, and 100℃.

Fig. 3.15 Projection lifetime of data retention with an Ea of 1.604 eV.

Chapter 4 Corner Effect of TFT-SONOS Memory Devices Following EOT Scaled Down

4.1 Introduction

In 2007, the main flash memory market combined NOR and NAND array have reached above $22 billion US dollars, economic forecast of the Non-Volatile Memory (NVM) market almost occupy above 45 percent of memory market in 2010, nearly 22 percent of the total semiconductor market. According to the Moor’s Law, the non-volatile memory has been leading the way from 16 Mb and 0.35 μm of technology node in 1994 to 32 Gb and 40 nm of technology node today [4.1].

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