The simulated annealing process begins from a random feasible Γ. We insert the buffer and flip-flop according to the method described in Section 3. Then we per-turbs the floorplan using the three perturbations. After each move, buffers and flip-flops are planned according to the new floorplan. The process terminates when the solution is frozen, the temperature is too low, or the runtime is too long.
The flow of our algorithm is summarized in Figure 4.1. In line 1, we first get a initial floorplan by random assign the B*-tree. In lines 3-16, we perturbs the floorplan from one to another until the solution is converged or cool down.
Figure 4.1: simultaneous buffer / flip-flop station planning and voltage drop.
Chapter 5
Experimental Results
We implemented our approach in the C++ Programming language and the platform is AMD Opteron (tm) 2.8G with 2.0GB memory. We experiment with our approach on MCNC[1] circuit banchmark. Table 5.1 lists the technology file and buffer library used in our experiments that are based on 0.18-µm in the NTRS’97 roadma[2]. The intrinsic delay and input capacitance of a flip flop is 10% that buffer has. Our IR-drop constraint is 5% of the supply voltage. Thus the IR-drop constraints are Vmin = 1.71 for the power and Vmax = 0.9 for the ground. We give each circuit two power pads and randomly assigned the peak current on each P/G pin of the modules as [15] did. The current of buffer and flip flop are assigned as the proportion of its area to the smallest module area in each circuits. The vertical and horizontal power wire pitches are both 600µm.
The first experiment compare the results of planning buffer block without IR drop consideration and our methodology that insert buffer block and also consider IR-drop. In this experiment, the two-terminal nets obtained by splitting from mul-titerminal nets and the timing requirement of each net are generated by [9] from 1.05-1.20Dopt as the [11] did. The experimental result are summarized in Table 5.2 . The first column shows the circuit name and the algorithm used. The second column shows the number of nets meeting timing requirements (# nets meet) and
Table 5.1: Parameter of 0.18-µm Technology in the NRTS’97 RoadMap[11].
Parameter Description (unit) Value
r wire sheet resistance (Ω/¤) 0.068
rw wire unit-length resistance of 0.9 µm width (Ω/µm) 0.075
ω wire width (µm) 0.9
cw wire unit-length capacitance of 0.9 µm width (Ω/µm) 0.118
CL load capacitance (fF) 23.4
RD driver resistance (Ω) 180
Db intrinsic buffer delay (ps) 36.4
Cb buffer input capacitance (fF) 23.4
Rb buffer output resistance (Ω) 180
Ab buffer size (µm2) 400
that of total nets in a circuit ( Tot. # nets). The third column gives the percentages of nets meeting the timing constraints. Column4 lists the number of buffers inserted (# buffers). Column 5 gives the worst voltage of modules in each circuit. Column 6 gives the percentages of extra areas over the given floorplans for buffer insertion.
The result shows that our methodology have almost the equal result on the timing requirement and the area overhead and also does not violate any IR-drop constraint.
In the second experiment, unlike the first experiment, the timing constraint for every net are given the same constraint to reflect that some nets need pipelining . Because the ami33 circuit is much smaller than others, its timing constraint is given as half value of other circuits. We compare our methodology ”simultaneous buffer / flip-flop station planning and voltage drop minimization in floorplan design” called method A (M. A) to the case that does not consider IR-drop called method B (M. B) and the case that does not consider latency and throughput called method (M. C).
The experimental result are summarized in Table 5.3. Column 4 lists the number of nets that only needs buffer (B. net). Column 5 lists the number of nest that are pipelined (FF net). Column 6 lists the number of buffer inserted (# B). Column
Table 5.2: Compare the result of planning buffer block and the result of planning buffer block considering IR-drop, where column 2 is the number of nets meet timing requirement / number of total nets, column 3 is the percentage representation of column 2, column 4 is the number of buffer inserted, column 5 is the smallest voltage of the P/G pin among the modules in each circuit, column 6 is the area overhead caused by buffer inserted.
# buffers worst voltage Extra area (%) apte
7 lists the number of flip-flops inserted (# FF). Column 8, 9 , respectively, are the worst latency and system throughput.
From the results of M. A, M. B, and M. C, it shows that our methodology can find a path with minimum latency if there exist any one (each percentage of nets meet timing requirement is high than 98%). The results of M. A and M. B shows that M. A does not have any IR-drop violation thought M. B have less area overhead.
The IR-drop violation and area overhead is a tradeoff between M. A and M. B. The Results M. C have almost equal overhead to M. A but have less system throughput and higher latency.
Table 5.3: Compare the result of planning buffer / flip flop considering IR drop (M.
A) and without IR-drop consideration (M. B) and without latency and throughput consideration (M. C), where column 4 is the number of nets that need only buffer to satisfy its timing requirement, column 5 is the number of the nets have to be pipelined, column 6 is the number of buffer inserted, column 7 is the number of flip flop inserted, column 8 is the largest latency of nets, column 9 is the largest throughput of cycles.
Chapter 6 Conclusion
In this thesis, we propose a methodology to pipeline interconnect in floorplan to estimate the system latency and throughput to avoid extreme high latency global net. Also we consider the IR drop during the planning of buffers and flip flops. The experimental results shows that our methodology is effective. As the size of chip getting larger, and size of buffer getting smaller, we expect the methodology will become more important in the future.
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作者簡歷
潘信華，民國七十一年七月出生於台北市。民國九十四年六月畢業於輔仁大 學電子工程學系，並於同年九月進入國立交通大學電子研究所就讀，從事 VLSI 實體設計方面相關研究。民國九十七年一月取得碩士學位，碩士論文題目為『在
佈局階段同時對緩衝器與正反器做放置規畫以及電壓下降的最小化』。