1.1.1 Placement
Regarding to current state-of-the-art, placement can be categorized to three cate-gories: partition based, linear force-directed and non-linear force directed. Partition-based placer such as Capo[21] partition the given placement using Fidducia-Mattheyes
in a top-down fashion. Although it does not require any model to approximate total HPWL, it trails behind force-directed and non-linear force directed placer in both quality and run time.
Non-linear forced directed placer such as NTUPlace3[9], mPL6[5] and APlace2[15]
uses log-sum-exp model to approximate total HPWL. The log-sum-exp model is a very accurate model to approximate HPWL. However, log-sum-exp model is rela-tively complex which requires longer run time and is patented which requires license to use. To accelerate run time, non-linear force directed placer generally coarsen the given placement by clustering cells to reduce problem size.
Linear force directed placer such as RQL[24], simPL[16], FastPlace3[25] and KraftWerk2[22] use bound-to-bound, star-net or clique model to approximate total HPWL. The simplicity of linear force directed model implies faster run time but is less accurate compare to log-sum-exp model. However, recent development in [24]
and [16] have outperformed all non-linear force directed placer in total HPWL by a notch and is approximately 3-5 times faster.
1.1.2 Thermal Model
Regarding to thermal model, most recent approaches can be categorized to nu-merical and analytical approach. Nunu-merical approach generally uses finite-difference method(FDM) [12] or finite-element method(FEM) [23] by meshing given silicon substrate and then solve a set of linear equation to obtain temperature profile. FDM discretizes the partial differential equation of heat conduction and uses forward-difference method to approximate temperature profile. FEM discretizes the given temperature for each grid point in design space and then points elsewhere is calcu-lated using interpolation. Generally, numerical approach can achieve high accuracy at the expense of relatively long run time making it suitable for post-layout thermal verification.
Analytical approach solves the differential equation of heat problem by first generating the fundamental solution of one unit heat source and then exploit the linearity of the heat equation to obtain the general solution of overall temperature distribution [27][26][13]. In contrast to numerical approach, analytical approach can quickly obtain an approximate solution in closed form representation without an amount volume of meshing making it suitable for where approximate solution is adequate.
After two classified approaches, there is two states of analysis to be concerned, transient-state and steady-state. The transient-state is concerned about ture in time-varying but the steady-state is interested in the stabilized of tempera-ture in long term state. In this paper, we proposed to consider the steady-state of temperature.
1.1.3 Thermal Aware Placement
To implement a thermal aware placement, two main components are usually required: a thermal model to conduct full chip thermal analysis and a placement mechanism to consider the optimization between thermal effect and wirelength.
Regarding to previous works on thermal aware placement, Table 1.1 summarizes previous work on thermal aware placer based on their thermal model and place-ment algorithm. Tsai et al.[23] constructs lumped RC matrix to model substrate heat conduction and obtain thermal profile using FDM, then simulated annealing is applied evenly spread out hot spot. Kahng et al. [14] adopts its thermal model from [23] and integrate the model to its previously published placer, APlace [15].
Chen et al.[8] simplifies the model in [23] and applies partition based placement to consider thermal effect. Goplen et al.[11] uses FEM method to conduct full chip temperature analysis and uses linear force directed placer based on star net model to mediate thermal effect. Jing et al.[17] constructs RC equivalent matrix to model
heat transfer and obtain thermal profile using FDM, Fiduccia-Mattheyses partition is then applied as their placement strategy. Bernd et al.[19] proposes a methodology to consider the impact of dynamic power density by adding additional temperature cost obtained from FDM into the iterative annealing optimization.
Table 1.1: Previous work on thermal aware placement
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In spite of past effort, thermal aware placement today still suffers deficiency in terms of (i). accuracy of full-chip analysis,(ii). quality of placement and (iii).
fast execution time. The accuracy of some thermal models are unknown since it lacks evaluation with accurate model. The quality of algorithms for placement is deficient either because it greedily focuses on thermal distribution or its placement methodology is relatively naive. Some methods are impractical to deal with million gate design due to execution speed when using simulated annealing or solving com-plex thermal model requires long execution time. In addition, none of our surveyed thermal-aware placers has tested on million gate design.
In this thesis, we presented a thermal aware placement to reduce maximum temperature using analytical thermal model combined with linear force-directed placer. Both of our thermal model and placer are analytical making it inherently fast. The run time bottleneck of Green function based thermal analysis is in its post-process DCT calculation and we reduced the complexity to O(N logN ) by applying even extension and input reordering algorithm. Our thermal model is verified with commercial tool ANSYS Icepak and demonstrated that the deviation of our thermal