As mentioned in Section 4.2, we can obtain the desired oscillating frequency by tuning the equivalent capacitance. In order to cover the process and temperature variation, the digitally controlled oscillator should have a large operation range.
Owing to many trade-offs between large tuning range and desired operation clock period, we develop a standard procedure to determine the DCO size called the normalization process.
As Figure 4.16 shown, a simple structure is used to illustrate the normalization process. We normalize the main fixed inverter to be “one”. Then we change the loading range of the coarse-tune stage from 0.1 to 1.5 and similarly change the loading range of the fine-tune stage from 0 to 6.3.
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Figure 4.16 The normalization of DCO structure
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Figure 4.17 shows The DCO output clock period simulation results when all control pins are all ones. The clock period of DCO output being greater than 970ps is what we want to meet process variation as Figure 4.17 shows.
Figure 4.17 The DCO output clock period simulation result when all control pins are ones
Figure 4.18 shows the DCO output clock period simulation results when all control pins are zeros. The clock period of DCO output being smaller than 640ps is what we want to meet process variation as Figure 4.18 shows.
Figure 4.18 The DCO output clock period simulation result when all control pin are zeros
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Figure 4.19 shows the tuning range simulation results at different fine-tuning loading condition. The rectangular range being marked is the desired DCO output clock range. In order to find out more precise ratio relationship, we take the rectangular range for more detail SPICE simulation.
Figure 4.19 Tuning range simulation result at different fine-tuning loading value Figure 4.20 shows the enlarged DCO output clock period simulation results when all control pins are ones. The clock period of DCO output being greater than 970ps is what we want as Figure 4.20 shows.
Figure 4.20 The enlarged DCO output clock period simulation result when all control pin are ones
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Figure 4.21 shows the simulation results when all control pin are zeros. The clock period of DCO output being smaller than 640ps is what we want as Figure 4.21 shows.
Figure 4.21 The enlarged DCO output clock period simulation result when all control pin are zeros
In Figure 4.22, there are most points satisfy our demands which include wide tuning range and wanted operation range. However, when N=0.8 we find the clock control range of each section is not wide enough that results in some gaps in SPICE simulation. Hence, we choose N=0.9 as our fine-tune delay stage ratio to avoid gaps.
Figure 4.22 Tuning range sim. at different fine-tuning loading value from 0.7 to 1.5
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Then, we want to find the ratio of parameter M when N=0.9. We slowly add the ratio of M from 0.1 to 1.5 to observe simulation results. As Figure 4.23 shown, we mark the desired range of the upper bound and the low bound, and we can find the ratio of M=1.25 satisfying our marked range.
Figure 4.23 Find the ratio of M to satisfy our desired performance
We find the ratio relationship 1:M:N=1:1.25:0.9 through normalization process as mentioned above. Follow this relationship, we propose our DCO architecture as Figure 4.24 shows. We can separated coarse-tune stage into four binary weighted increment segment controlled though digital control word. Similarly, fine-tune stage can be separated four binary weighted increment segment controlled though digital control word. The LSB bit of every stage is controlled independently. In this way, we obtain 4 times resolution promotion. Therefore, we need a decoder circuit to obtain thermometer code control. We draw true table and the decoder circuit as Figure 4.25 shows. S3 is always turned off. S2 is obtained through the AND of a0 and a1. S1 connected to a1 directly. S0 is obtained through the OR of a0 and a1.
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Figure 4.24 Our proposed DCO architecture
Figure 4.25Decoder circuit
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Figure 4.26 shows monotonic curves of tuning codes according to coarse and fine tuning of the DCO. The frequency range is 1.06GHz-1.56GHz at TT corner. And delay range of the fine delay chain is about 34.56ps. Therefore, the resolution is about 0.54ps.
Figure 4.26 Frequency range of the proposed DCO
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Figure 4.27 shows the delay resolution of the fine-tuning stage and the proposed delay cell has finer resolution (about 0.54ps) than JSSC’03 [12]. OAI cell [12] has less transistor counts and less power consumption, but it has non-uniform linearity.
Figure 4.27 Linearity and resolution comparison
The operation range of the digitally controlled oscillator is shown in Figure 4.28 and 4.29. Figure 4.28 shows the clock period of DCO output at three different corner cases. Figure 4.29 shows the clock frequency of DCO output at three different corner cases. Table 4-1 summarize the features of the proposed DCO.
Table 4-1 The features of proposed DCO
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Figure 4.28The clock period range of DCO at three different corner cases
Figure 4.29The clock frequency range of DCO at three different corner cases
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Chapter 5
ADPLL System Design
In chapter4, we have designed and analyzed the proposed DCO. After designing the DCO, we must design a control mechanism to control the DCO to oscillate at the desired frequency. Thus, we must compare the frequency difference and detect the phase difference between the reference clock and the feedback clock. In this way, the control unit can produce accurate control signals to dictate the frequency of the DCO.
The control unit, frequency comparator and phase detector are all digital functional blocks. [16] shows some examples about the frequency phase detector and control unit . A specific control unit only controls a specific DCO and only receives specific signals produced by the FD or PD. Besides, search algorithm is also another important issue. We use improved binary search as our search algorithm which is the soul of our ADPLL system. In this chapter, we will introduce search algorithm, control unit circuit, and simulation results.
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