The factors driving passive integration technology include higher operating frequencies, which require smaller parasitics than discretes can provide, and overall system miniaturization and/or functionalities (i.e., higher component/packaging density and/or parts count). MLO technology has the potential for achieving denser packaging, more efficient manufacturing processes, better reliability and future replacement of many surface mount devices that will result in savings of volume, weight and cost.
From the above results, the embedded passive components with MLO technology exhibit some limitations in RF applications, which still require further improvements in materials and processes. To cover the inductance range in wireless applications, the designed embedded inductor should be improved. The development of HDI substrate as an enabling technology for improving the circuit density, electric characteristics and integrating passives components is noted. By means of the fine line/spacing resolution and microvias, the interwinding magnetic flux leakage of embedded solenoid inductor could be improved. In addition, high permeability materials with partial filled (i.e., core filled) process to further decrease magnetic leakage, high dielectric constant to increase capacivity and low dielectric loss to improve Q-factor are still needed for applications in high frequency system.
Fig. 2.1 Magnitudes of S12 and S21 of 500 mils and 1000 mils through lines used in the multi-layer TRL calibration experiment.
Fig. 2.2 Phase response of 500 mils and 1000 mils through lines used in the multi-layer TRL calibration experiment.
lstub
Fig. 2.3 Structure of a T-resonator.
Fig. 2.4 Example frequency response of S21 of a T-type resonator.
Fig. 2.5 Structure of split-cavity resonator.
Fig. 2.6 Layer assignment of the 6-layer PCB test board.
Thickness of Cu: 1 oz. Unit: mil
1st metal signal 2nd metal GND 3rd metal signal 4th metal signal 5th metal VCC
6th metal signal
3.5
6.2
3.5 3.7
3.7
2nd substrate high dielectric
4th substrate high dielectric
1st substrate FR-5
3rd substrate FR-5
5th substrate FR-5
Split cavity Material sample
(a)
(b)
Fig. 2.7 Structures of: (a) 2-layer MIM capacitor and (b) 4-layer MIM capacitor.
Fig. 2.8 Lumped-element model of a MIM capacitor.
W
Metal
High dielectric material W
W
C R
Cg Cg
LP LP
High dielectric material via
W Metal
General substrate
Fig. 2.9 The capacitance vs. dimension for the multi-layer MIM capacitors.
Fig. 2.10 Structure of a N-turn solenoid inductor.
100 200 300 400 500 600
W (mil) 0
200 400 600 800 1000 1200
Capacitance (pF)
4-layer MIM 2-layer MIM
N turns
Via M1
M2
D
D
S
Fig. 2.11 Lumped-element model of a solenoid inductor.
Fig. 2.12 The inductance vs. number of turns for the solenoid inductor.
R L
CP
Rg Rg
Cg Cg
0 1 2 3 4 5 6
Number of turns 0
1 2 3 4
Inductance (nH)
CHAPTER 3
DESIGN OF MINIATURIZED COMMON-MODE FILTER BY MULTI-LAYER LOW TEMPERATURE CO-FIRED
CERAMIC
3.1 Introduction
With increasing demands on system functionality and data storage, higher data rate in electronic devices is requested. In proportion to the higher operating speed and frequency band, more unwanted electromagnetic radiation is introduced.
High-speed data transmission together with ever-lower logic threshold voltage makes today’s electronic sets extremely vulnerable to the problem of unwanted noise. In high speed transmission, signal integrity of the transferred data is a critical issue, even total system may suffer from malfunction when sufficient radiation noise is picked up by the interface cables or digital devices [24].
In high-speed data communication, differential signaling has found increasing applications (e.g., IEEE 1394, USB 2.0, Gigabit Ethernet, and so on). When two equal-amplitude and 180 degrees out of phase signals are transmitted through a pair of traces, with which a signal on a trace is designed to reference to the signal on another trace, it is operating in a differential signaling scheme. The two traces are known as a differential or balanced pair. In principle, by this electrically symmetrical referencing architecture, common-mode noise picked up by the differential pair will be subtracted. For this reason, differential circuit inherently exhibits better immunity to noise and has been therefore gaining popularity in recent years as data rate demand increases.
Although the ideal differential transmission pair can enhance the immunity capability in noisy environment, discrepancy occurs in delay or path loss between the paired traces, following imbalanced phase and/or amplitude resulted in the source, load, or the circuit path, common-mode current will be introduced [28]. These currents are conducted on the differential pair in the same direction and can act as dominant source of radiated emission at high frequencies. Several published papers [29]-[32] have investigated and analyzed the common-mode current influences. To comply with the various EMC standards, these common-mode currents need to be restricted and suppressed low enough.
Common-mode toroid choke, in the form of 1:1 longitudinal transformer, is one of the most general methods used to reduce common-mode current [33]. Such a choke is actually a 1:1 transformer consisting of a pair of coils wound around a common ferrite toroid. The effectiveness of the common-mode toroid choke relies on the assumption that the high permeability makes the self and mutual inductance equal. In the ideal conditions, the differential-mode current flow through both windings in opposite directions which generate two mutually canceling magnetic fluxes, with their loading effects represented by the subtracting self-inductance and mutual inductance, thus the functional signal can ideally pass the magnetic core smoothly and only be attenuated by ohmic resistances of traces and core material.
The common-mode current however, by virtue of additive magnetic fluxes, is effectively “choked” as a result of the complete magnetically coupled high common-mode inductance. The higher permeability ferrite cores can concentrate more flux in the core and reduce any leakage flux. At frequencies on the order of GHz or more, the highly degraded effective permeability and severe material loss of ferrite core might compromise the effectiveness of such ferrite choke. Furthermore, the short wavelength of high frequency signal may become comparable to the
electrical length of the choke coils. Consequently, any small variation in reproducibility of coils and ferrite material may result in significantly degraded performance. Further, the size of the toroid is difficult to reduce, which contribute to effort toward developing alternative multi-layer structures with much improved process tolerance and high-frequency material loss [34], [35].
In this chapter, the design of a common-mode filter using multi-layer LTCC technology for high-data-rate-applications is presented. The design is to achieve sufficient common-mode suppression while introducing minimal pass-band insertion loss and mode conversion to the desired differential-mode signal. This chapter consists of following aspects: in Section 3.2, the designing and equivalent circuit modeling of multi-layer LTCC common-mode filter is presented first, which is followed by the miniaturized offset design. Section 3.3 discusses the extraction of the equivalent circuit model parameters and illustrates some measured results with the specifications defined at USB-IF (http://www.usb.org/). Finally, Section 3.4 gives a summary and some concluding remarks.
3.2 Design and Modeling
3.2.1 Equivalent Circuit Model of Multi-Layer Common-Mode Filter
Figure 3.1 shows the structure of multi-layer common-mode filter and its equivalent circuit model, which is represented as a coupled equivalent lumped-circuit, is demonstrated in Fig. 3.2. The multiple equivalent lumped-circuit sections are used to represent the plurality of differential pairs in the designed multi-layer structure. Each section contains a pair of coupled inductances LS with series resistances RS accounting for wiring resistance, shunt resistance RP signifying the dielectric loss, and a parallel capacitance CP representing capacitive coupling between positive and negative coils in adjacent layers. In addition, series capacitance CS
denotes the parasitic winding capacitance of each coil. The grounded R and shunt L-C of each trace account for antenna effect of the distributed solenoid coil and
parasitic coupling between coils and the ground plane of the test board. The magnetic coupling between adjacent differential traces is represented by the coupling coefficient K. With equal vertical spacing (i.e., layer thickness) D of each differential pair, the coupling coefficient K is assumed to be equal for all sections.
The equivalent lumped inductance and resistance LS and RS are directly proportional to the length of the coil on each substrate. At higher frequencies, equivalent lumped-circuit representation of a distributed transmission line dictates the use of more than one section per layer. This can be done in a straightforward manner, details of which are therefore skipped here.
The typical single-ended scattering parameters (S parameters) are not sufficient to accurately characterize a differential component operating in differential mode. To have a solid analysis on a differential device, mixed-mode S parameters are introduced [36]. The generalized mixed-mode S parameters can be given as:
bdm1 = sdd11adm1 + sdd12adm2 + sdc11acm1 + sdc12acm2
bdm2 = sdd21adm1 + sdd22adm2 + sdc21acm1 + sdc22acm2
bcm1 = scd11adm1 + scd12adm2 + scc11acm1 + scc12acm2
bcm2 = scd21adm1 + scd22adm2 + scc21acm1 + scc22acm2 (3.1)
where admn and acmn are the normalized differential- and common-mode incident waves from port n, bdmn and bcmn are the corresponding normalized differential- and common-mode reflected waves. With mixed-mode S parameters, a complete characterization of the multi-layer common-mode filter, including the differential-mode, common-mode, and any mode conversion responses, are revealed.
The general 4-port single-ended S parameters can be converted to 2-port mixed-mode S parameters by using the circuit shown in Fig. 3.3 [37]. To perform the differential-mode conversion and provide the mechanism for the common-mode terms, a center-tapped balun is used. The common-mode conversion occurs at the center tap of the balun where only common-mode signals will appear because of the characteristics of the balun. These common-mode signals are then terminated through a balun into common-mode port. By applying this configuration, differential device represented by general 4-port single-ended S parameters are converted to 2-port mixed-mode parameters first. Subsequently, the parameters associated with the equivalent circuit of Fig. 3.2 are extracted and used to fine-tune the structural parameters for the optimization of differential- and common-mode performances and the minimization of component size.
3.2.2 Design of Multi-Layer Common-Mode Filter
Exploring the significant recent advances in the LTCC process techniques for high frequency application, a multi-layer structure using ceramic substrate with relative permeability 1, relative permittivity 4.8, and dielectric loss tangent 0.0016, is designed by employing symmetric structure similar to, but without the drawbacks of, wire-wound common-mode choke. By using longer coupling traces, the lower permeability and the resulting smaller inductance as compared to ferrite material can be compensated. To have long coupling traces, a 3-D multi-layer structure with multi-turn square spiral on each layer is formed. Each substrate is printed with conductive silver coil pattern and via holes. Positive coils and negative coils are formed on alternate substrates. After all the substrates are stacked, each positive coil is then connected in a sequence through the first plurality of via holes.
Similarly the negative coils are connected as a sequence through the second plurality
of via holes.
In such design, the dielectric and conductor losses are minimized; so any functional signal deterioration may occur mainly from signal reflection [34]. To achieve negligible effect on the transition edges (i.e., the high-frequency components) of differential digital signal, optimized characteristic impedance matching is needed.
With good differential signal matching, the insertion loss incurred on the functional signal, evaluated by Sdd21 of the mixed-mode S parameters, will be minimal over its intended operating bandwidth such that differential signal passes through the component undisturbed.
To design such optimum differential mode impedance, a full-wave, 3-D finite element method (FEM) simulator HFSS (Ansoft, Pittsburgh, PA) was utilized. As a first example, the spiral patterns in all layers are perfectly aligned. The line width W, horizontal trace spacing S, vertical spacing between positive and negative coil in each differential pair D, and vertical spacing H between adjacent differential pairs, as shown in Fig. 3.1, are parameters used to design an optimized matching. In principle, for the given W and S, different D and H combinations can be used to design different characteristic impedances by varying K and CP. For simplicity, D and H are assigned the same value. Using USB 2.0 as an example, the 90 ohms differential characteristic impedance can be obtained with W = S = 75 µm and D = H
= 140 µm. Figure 3.4 depicts the designed filter composed of 4 sets of differential pair and the input/output terminations. To compensate the difference in electrical length of the two differential traces so as to maintain phase balance, one additional layer (i.e., layer M9) for trace length compensation is added.
The simulated results of the designed multi-layer common-mode filter with mixed-mode S parameters are shown in Fig. 3.5. The Sdd21 curve represents the insertion loss of differential signal, Sdd11 curve denotes the reflection coefficient of
differential signal, and Scc21 is the attenuation of common-mode signal. With both conductor and dielectric losses considered in the simulation, this designed filter provides better than 10 dB common-mode attenuation over the frequency range from 0.273 GHz to 1.74 GHz, very low differential-mode insertion loss of Sdd21 > - 0.2 dB up to 1.7 GHz, and good differential-mode matching with Sdd11 < -10 dB up to 2 GHz.
To confirm the symmetric property of the multi-layer design, mode conversion S parameters Scd21 and Sdc21 are simulated and shown in Fig. 3.6. The small value, less than -20 dB, in the entire frequency band ensures the negligible mode conversion is achieved in the designed filter. So only little input energy is converted from differential signal to common-mode noise (i.e., evaluated by Scd21) and only insignificant fraction of input power is transferred from common-mode noise to differential signal (i.e., analyzed by Sdc21) at the output of the component. Given such performances, the designed common-mode filter appears capable of supporting broadband differential signaling while simultaneously suppressing the unwanted common-mode noise.
The designed filter is fitted in an EIA 1206 form factor (i.e., surface dimension 3.2 mm × 1.6 mm). The total occupied component thickness with 12 µm conductor thickness and the 10 foil substrates is 1.508 mm. It becomes an unusually thick component and a serious problem with which is that, with the width and thickness being almost equal, it is not convenient to differentiate the orientation of component and therefore not suitable for SMT assembly. Novel design to shrink the component thickness is thus required.
3.2.3 Miniaturization of Multi-Layer Common-Mode Filter
In the previous design, the positive traces and negative traces in alternate layers are completely overlapped in vertical direction as depicted in Fig. 3.7(a). The
differential-mode characteristic impedance of the transmission pair is determined mainly by the stray inductance and capacitance of traces. Equation for differential-mode characteristic impedance Z0d can be expressed as follow:
p p
where K represents the magnetic coupling coefficient between the two differential traces and rs, rp, ls, and cp are the per unit length series resistance, parallel resistance, stray inductance, and stray capacitance of the transmission lines, respectively. The self-inductances of each winding are represented by L and the mutual inductance is represented by M.
To shrink the thickness of component, a thinner substrate is needed. The thinner the substrate, however, the larger the parasitic capacitance cp is introduced and lowered Z0d would result if unattended. Solutions used to overcome the large parasitic capacitance include narrowing the overlapping traces and/or using lower dielectric constant material. However, with the general process capability nowadays, forming the narrower traces is difficult to perform. In the other solution, even with the lower dielectric constant material (i.e., εr = 4.3 is the dielectric constant available for the state-of-the-art LTCC process) applied, it was not found to result in significant decrease in the component thickness.
Alternatively, the capacitance associated with thin substrate can be lowered by horizontally displacing the originally overlapping traces, that is, an offset design is applied. As shown in Fig. 3.7(b), for a given layer thickness D, when the horizontal offset (T) between traces in adjacent layers increases the capacitance between traces
decreases. For a given capacitance, the larger the offset distance, the thinner the substrate foil can be used, which should result in a reduction in the overall thickness of the component.
Figure 3.8 demonstrates the simulated result for the offset structure. A 90 µm foil substrate with a 75 µm offset distance is employed in this design. As can be seen in the figure, Sdd11 remains lower than -10 dB from DC to 2 GHz. Also, Sdd21 is better than -0.2 dB at the operation frequency (i.e., 240 MHz) and its higher harmonics. For noise elimination, Scc21 is better than 10 dB from 0.239 GHz to 2 GHz. From 0.49 GHz to 1.11 GHz, the attenuation on common-mode noise is even larger than 20 dB. To check its mode conversion performance, Scd21 and Sdc21 are simulated and displayed in Fig. 3.9. Comparing Figs. 3.6 and 3.9, one can see that asymmetry between the displaced traces results in poorer, but yet acceptable (i.e., better than –20 dB), mode conversion performance. Comparing Figs. 3.5 and 3.8, it is concluded that, while offering comparable or even better performance, the filter designed with offset concept has an overall thickness of 1.008 mm, which is 33% less than the original design using completely overlapping traces.
3.3 Results and Discussion
3.3.1 S-Parameter Measurements and Extractions of Equivalent Circuit Parameters
According to the two different multi-layer designs mentioned above, samples are fabricated by LTCC process and measured by using an Agilent E5071B ENA series 4-port vector network analyzer. An SOLT (Short-Open-Load-Through) calibration is performed first to de-embed the measurement system and to shift the reference plane to the input/output connectors. To measure the fabricated components, a test board made of FR-4 with 4 feeding traces is applied. By the identical simulated 2-port S
parameters of the 4 feeding traces, the effect of the test board is de-embedded.
Figure 10 demonstrates the good agreement between the simulated and measured results of the offset design.
Due to the long trace length (about 15 mm) on each layer, a multiple sections equivalent circuit is required to obtain a representative equivalent circuit model at high frequency. To extract the parameters of elements used in the equivalent circuit model, the individual inductor is simulated and characterized first [18]. As depicted in Fig. 3.4, the input pair arranged on the top pair of foils (i.e., M1-M2) has shorter length than the internal pairs (i.e., M3-M4 and M5-M6); this is also the case for the bottom output pair (i.e., M7-M8). For simplicity, the circuit parameters associated with the compensated length on the bottom layer M9 is combined into that of the last pair. With these extracted parameters, LS and RS of each inductor, the coupling coefficient K, and parasitic capacitances CS and CP are then derived by curve fitting.
The simulated mixed-mode S parameters Sdd21 and Scc21are simultaneously fitted with the equivalent circuit. Finally, the value of insulation resistance RP is used to adjust the attenuation depth on the resonance frequency of Scc21.
As displayed in all simulated and measured figures, at 1.74 GHz an abrupt change occurs both on Sdd21 and Scc21. By checking the power conservation, it’s found to result from an inefficient antenna effect of the long distributed solenoid coil and parasitic coupling between coils and the ground plane of the test board [38].
The grounded R and shunt L-C resonator, as shown in Fig. 3.2, is applied to signify these phenomenons, respectively. With 3300-ohm radiation resistance and resonator composed of 820 nH inductance and 0.01 pF capacitance, Fig. 3.11 demonstrates the good agreements of Sdd21 and Scc21 between the equivalent circuit model and the simulated results. By means of 4 cell sections of the equivalent circuit as shown in Fig. 3.2, it can accurately model the electrical behavior of the filter to 2 GHz.
Figure 3.12 compares the simulated results of filters designed with original thick substrates and new offset design with thin substrates. Clearly, very comparable electrical characteristics on common- and differential-mode signals are observed for the two different designs. Table 3.1 summarizes the extracted parameters of the equivalent circuit model with and without offset design. As depicted in the table
Figure 3.12 compares the simulated results of filters designed with original thick substrates and new offset design with thin substrates. Clearly, very comparable electrical characteristics on common- and differential-mode signals are observed for the two different designs. Table 3.1 summarizes the extracted parameters of the equivalent circuit model with and without offset design. As depicted in the table