In this thesis, we proposed a configurable LDPC decoder for IEEE 802.11n and 802.16e. First, we analyze LDPC decoding algorithms for 802.11n and 802.16e and improvement spaces for row-update message passing, Belief Propagation, and Min-Sum algorithm, etc. According to simulation results by C-language, we decide normalization factor, number of iteration, bit width and other parameters for hardware implementation. A trade-off between hardware complexity and decoding performance is analyzed to decide the parameters. A configurable, partially parallel architecture with Zf parallelization is proposed to apply row-update message passing algorithm with min-sum. Some design considerations are discussed and solved by the proposed methods.
For adaptive code rates and code lengths, a point based permutation is designed to merge 22 types of Zf’s for 802.11n and 802.16e. Besides, parallel multi-codeword decoding technique for preserving high hardware utilization and early termination
mechanism to save power are considered. Multi-codeword decoding technique not only increases hardware utilization but also throughput when decoded codeword is less than 1152 bits (Zf < 48). Moreover, a flexible control provides users to decide whether turning off early termination or not for adaptive code rates and transmission channel.
The design is implemented in TSMC 0.13 μm 1P8M CMOS technology. The core size is 2.14×2.14 mm2 and die size is 2.69×2.69 mm2. The decoder operates at 333 MHz with 10 iterations for different code rates and code lengths. It has a peak throughput of 590 Mb/s and power dissipation of 451 mW for code rate 5/6, code length 2304 bits in 802.16e. In 802.11n, its peak throughput is 506 Mb/s with power dissipation of 436-mW for code rate 5/6, code length 1944 bits.
In low power mode, we divide operating frequency by 5 to 66 MHz to meet the required minimum throughput, 30 Mb/s for 802.16e. It has throughput 42.6~118 Mb/s for different code rates and code lengths. Power dissipation is lower to 86~101 mW for 802.16e in low power mode.
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作者簡歷
姓名：劉士賢 出生地：台南縣
出生日期：1983 年 3 月 12 日
學歷：1989. 9 ~ 1995. 6 台南縣立龍潭國民小學
1995. 9 ~ 1998. 6 台南市私立長榮高級中學 國中部 1998. 9 ~ 2001. 6 台南市私立長榮高級中學 高中部 2001. 9 ~ 2005. 6 國立交通大學 電子工程學系 學士 2005. 9 ~ 2007. 8 國立交通大學 電子研究所 系統組 碩士