Chapter 4 Matlab Simulation
4.2 Simulation Results
To evaluate the performance of proposed packet detection and symbol timing estimation, IEEE 802.11g PHY based on dual modulation OFDM and DSSS [1][2] is considered. The simulation environment is under Rayleigh fading channel with RMS 50ns and CFO 50 p.p.m. The results are obtained by applying 2000 simulation runs with different SNR.
Figure 4.2 and 4.3 shows the packet detection performance at 20 MHz first. The required SNR for packet loss probability equal to 1% is about 1.5 dB under different channel conditions. The required SNR for packet false alarm probability equal to 1%
is about 1~2 dB under different channel conditions.
-3 -2 -1 0 1 2 3
10-3 10-2 10-1 100
SNR Pbabyroilit
CFO 0 NO MULTIPATH CFO 50 NO MULTIPATH CFO 50 SPW11a
Figure 4.2 OFDM packet loss probabilities at 20 MHz
-4 -2 0 2 4
10-3 10-2 10-1
SNR Pbabyroilit
CFO 0 NO MULTIPATH CFO 50 NO MULTIPATH CFO 50 SPW11a
Figure 4.3 OFDM packet false alarm probabilities at 20 MHz
Figure 4.4 and 4.5 show the packet detector performance at 10 MHz. The required SNR for OFDM packet loss probabilities equal to 1% is 5.7 dB. The required SNR for DSSS packet loss and false alarm probabilities equal to 1% are -0.5 dB and -2.8 dB.
2 4 6 8 10
10-4 10-3 10-2 10-1 100
Pbabyroilit
SNR
Packet Loss False Alarm
Figure 4.4 OFDM packet detection at 10 MHz
-8 -6 -4 -2 0
10-3 10-2 10-1 100
Pbabyroilit
SNR
Packet Loss False Alarm
Figure 4.5 DSSS packet detection at 10 MHz
Figure 4.6 and 4.7 shows the symbol timing performance of two multi-path models SPW11a channel and IEEE fading channel. The packet loss and false alarm probabilities are very close in both channels. But the symbol timing error probability in IEEE fading channel is larger than in SPW11a channel. The performance loss is due to the pre-cursor channel impulse response.
2 4 6 8 10
Figure 4.6 Symbol Timing Error in SPW11a channel
2 4 6 8 10
Figure 4.7 Symbol Timing Error in IEEE fading channel
Chapter 5
Hardware Implementation
5.1 Fixed Point Simulation Result
Figure 5.1 illustrate the fixed point simulation result. The simulation environment is under SPW11a fading channel with RMS 50ns and CFO 50 p.p.m. The results are obtained by applying 1000 simulation runs with different SNR. The data rate is 6 Mbps and PSDU length is 500 bytes. The required SNR for PER 8% is about 6.6 dB for both float-point and fixed-point, which satisfy the standard requirement.
5 5.5 6 6.5 7 7.5 8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
SNR PE
R
PER (Float-Point) PER (Fixed-Point)
Figure 5.1 PER versus SNR with float-point and fixed-point
5.2 Matlab to Verilog Design Flow
To make sure that the Verilog behaviors 100% match Matlab simulation results, several things must be confirm. We show the flowchart of Matlab to Verilog design in figure 5.2. At First, we must find out the word length of variables in the Matlab platform, due to variables in Verilog only have finite precision. Fixed-point simulations are performed to ensure that these changes will not degrade system performance serious. It is trade-off between cost and performance. Second, once the fixed-point simulations are done, we use Matlab to generate input and output data of desired Matlab function, and feed the input data to the designed Verilog function. If the output data of Matlab are completely the same as the ones of Verilog, the Matlab to Verilog design is done.
Fixed-Point
Fixed-Point Matlab Function
Fixed-Point
Verilog Module
Verilog Test Bench
Correct?
Matlab Output Pattern
Verilog Output Patten Input Pattern
Yes Modify code No
Done Float-Point
Matlab Function
Start
Figure 5.2 Flowchart of Matlab to Verilog design
5.3 Design Architecture
The whole architecture of the proposed algorithms can be divided into three parts, the OFDM packet detection, DSSS packet detection, and OFDM symbol timing estimation. The block diagram of OFDM/DSSS packet detection is depicted in figure 5.3. The detection control consist of two small self-run FSM, one for OFDM packet detection, and the other for DSSS packet detection. At first, the data are saved into 32-element shift registers. The OFDM packet detection, DSSS packet detection, and the OFDM symbol timing estimator share the shift registers.
C
Figure 5.3: block diagram of OFDM/DSSS packet detection
Figure 5.4 shows the architecture of OFDM packet detection. The architecture of OFDM packet detection can be implemented with the iterative formula by transform the equation (3.1) and (3.2) into
Thus, we can save a lot of adder and complex multiplier into only one adder, one complex multiplier, and extra shift registers to save the subsequence calculations. And these calculations are rounded to nearest integer before further usage. The FSM control SEL_10M to indicate the current sampling rate, 10 MHz or 20 MHz. If the sampling rate is 10 MHz, one short preamble only consists of 8 samples. The output of complex multiplier is the autocorrelation of one sample and the square value is the corresponding power. The square part can be implementing with Look-up Table (LUT) rather than multiplier to reduce hardware cost. The auto-correlation and power of one sample are saved in the Corr_FIFO and Power_FIFO, respectively. According to equation (5.1) and (5.2), the summations in equation (3.1) and (3.2) are replaced with accumulation. Finally, the criterion for OFDM packet detection can be achieved by comparing the auto-correlation c(t) and received power p(t), as mention in equation (3.4). The comparison results are sending to the OFDM FSM to generate the control signal.
ADC_in
Figure 5.4 Architecture of OFDM Packet Detection
Figure 5.4 shows the architecture of DSSS packet detection. The Barker peak is obtained by de-spreading the received data with 11-chip Barker sequence. And then the data path can be divided into two branches. The upper branch is to calculate the
“Peak” in equation (3.7). First, it finds every max peak in each window, and then checks the interval of every adjacent peak to see if the interval is the same as 100 ns.
The lower branch is to calculate the “Valley” in equation (3.7). It utilizes a shifter register to calculate the summation of “Valleys”. Finally, the “Peak” value and the
“Valley” value are compared, and the results are used by the DSSS FSM to make the decision.
Figure 5.5 Architecture of DSSS Packet Detection
If both detector claims simultaneous, the OFDM packet is declared in consequence of the length of OFDM preamble is much shorter than DSSS preamble.
Figure 5.5 shows the architecture of OFDM symbol timing estimator. The data in shift registers are correlated with a pre-known long preamble, we only user the first half of long preamble, which are 32 samples. After that, the correlation value is used to calculate the ξmax and a counter λ(t) in equation (3.13) and (3.14).
ADC_in
3 2 1
syncBuffer _in 32 regs 32 31 30
CL-1 CL-2 CL-3 C3 C2 C1
1 2
* 0
( ) ( ) ( )
LL
k
t r t k LT k
−
=
ξ =
∑
+argmax Sym.
Timing
( )2 LUT
Figure 5.6 Architecture of OFDM Symbol Timing Estimator
5.4 Implementation Result
An IEEE 802.g PHY receiver is implemented to verify the feasibility. Table 5.1 lists the chip characteristics of the IEEE 802.11g PHY receiver. The process is UMC .13um standard cell library and Cadence BGX is used for the synthesis. The maximum available clock rate is 20 MHz and the area of synchronizer is 82105 um2, about 20k gate counts. The implantation loss is slight and conforms to the requirements. In addition, the proposed synchronizer is applied in the chip of 11g baseband receiver by isIP Lab as demonstrated in the Figure 5.6. Due to we only have limit area, the shape of layout is rectangle.
Table 5.1: IEEE 802.11g PHY receiver chip characteristics Process UMC .13um standard cell
PAD Number 43 pins (PAD limit)
System Clock 20 MHz
SYNC TOTAL
Gate Count 20 K 170 K
SYNC
Figure 5.7 Layout of 802.11g PHY receiver
Chapter 6
Conclusion and Future Work
6.1 Conclusion
In this thesis, we propose a packet synchronizer that can handle successful both OFDM and DSSS packets in dual-mode (OFDM/DSSS) systems with only one set of ADCs and dynamically controlling the sampling frequency. By this way, we can achieve the low-power approach in the wireless baseband processor, whereas keep the overall performance met standard requirements. Not only the algorithm itself, but also the parameters of algorithm, threshold decisions, are carefully discussed. The threshold decision is as important as the proposed algorithm. To hardware implementation, the fixed-point Matlab simulations decide the word length of every module. According to the fixed-point simulation result, a test chip using 0.13 um technology is implemented to verify the feasibility.
6.2 Future Work
There are some possible improvements in the future works. First, although the ADPLL can dynamically controlling the sampling frequency, the practical and detail behavior of ADPLL are not considered in this thesis. We just assume that the sampling frequency will change as soon as we want. But it is impossible in a real world, and there will be some transaction time and jitter will occur. So a detailed ADPLL model is necessary in the Matlab simulation. Once the ADPLL model is constructed, a real ADPLL can be hardware implemented in the proposed packet synchronizer. Second,
the adaptive threshold decision as mentioned in subsection 3.3.1 is a good approach to further improve the performance and robustness in packet detection. In the adaptive threshold approach, the threshold can adapt to the channel condition, and the false alarm and packet loss probability can be reduced.
References
[1] Supplement to standard for LAN/MAN part 11: Wireless MAC and PHY specifications:
High-speed physical layer in the 5GHz band, IEEE 802.11a, 1999.
[2] Supplement to standard for LAN/MAN part 11: Wireless MAC and PHY specifications:
Higher-Speed Physical Layer Extension in the 2.4GHz Band, IEEE 802.11b, 1999.
[3] Multi-band OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a, IEEE P802.15-03/268r3, 2003.
[4] DS-UWB Physical Layer Submission to 802.15 Task Group 3a, IEEE P802.15-04/0137r3, 2004.
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2001
[6] Timothy M. Schmidl and Donald C. Cox, “Robust Frequency and Timing Synchronization for OFDM”, IEEE Transactions on Communications, Vol. 45, NO. 12, Dec 1997
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12, Dec 2001
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[9] Shih-Lin Lo, “The study of Front-End Signal Process for Wireless Baseband Applications
＂, NCTU, master thesis, June 2003
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