6 Readout chips
6.2 Skiroc2cms
Skiroc2cms has 64 channels. Half of these channels are connected to the silicon sensor, while their twin channels which lie in the same position are left unconnected. Both fast and slower shaper circuits are readout in 2017/2018 period. However, only the slow shaper circuits are used in the charge measurement. The functionality of the slow shaper remains the same(10:1 HG and LG circuits) while there is a new circuit called Time Over Threshod(TOT). Another circuit, the Time Of Arrival (TOA), is also included for providing a precise (∼ tens of pico-second resolution) timing measurement. 10-bit DAC threshold can be set in both TOT and TOA. TOT is designed to cover the signal range even after the LG circuit is saturated so that the dynamic range set in HGCal TDR (1 fC
∼ 10 pC) can be fully covered. With HG, LG and TOT circuits for signal measurement and TOA circuits for timing measurement, the HGCal prototype has a chance to realize the original purpose for a 5D detector (energy, time, x, y, z).
Both connected and non-connected channels(HG,LG,TOT and TOA) are readout and stored for analysis purpose, mainly for noise study.
6.2.1 Skiroc2cms single moudule data taking
At the time the module arrive CERN, a reception test via a special designed system was performed. This system, shown in Figure 6.1, have the ability to execute the data taking of a single module and decode the data from the chip at the same time. The connection to a display is also available. The raspberry Pi 3 (RPI3) serves as the CPU of the test system, which can communicate with the MAX10 FPGA on the test stand. The MAX10 FPGA can then pass the order from the PRI to the FPGA on the module PCB thus the data taking and readout can be achieved.
Figure 6.1: Single module test system
This is the test system at NTU, but identical to the test stand at CERN.
In each event, 30 numbers are recorded to reconstruct the pulse for every channel. The number “30” is given by 13 ADC counts in both highgain(HG) and lowgain(LG) plus 2 TOTs(slow shaper and fast shaper) and 2 TOAs(falling and the rise edge of the system clock).
The 13 ADC counts come from 13 SCA(Switched Capacitor Array) units in the chan-nel, which sample the input pulse every 25 ns.
During acquisition, an 8 bit word is read from the MAX10 FPGA each time. In every 8 bit words, the first 4 bits are given by the on-board FPGA and the later 4 bits come from the 4 Skiroc2cms (one bit for each CHIP).
The MAX10 will send 30787 (8 bit)words in a single event, while the first word is the header and the last 2 words are blank just to label the end of the event. Other 30784 words in the middle are the collected data.
Since each 8 bits word correspond to 1 bit data in the CHIPs, there are 30784 bits in total for each CHIP in a single event. These bits will be decoded into 30784/16 = 1924 16-bits words in the end. The number “1924” is exact the 30 numbers recorded in
64 channels, plus additional 4 words to describe the event (30 number × 64 channels = 1920).
The last four 16-bits words in the map will be:
1. Roll position: records which SCA is “in use” when the trigger signal arrive.
2. Global time stamp(TS) MSB
3. Global TS LSB - combine MSB and LSB we record the global time of the trigger signal
4. CHIP ID: a fixed number in beam test
After the decoding process, one can get the “1924” numbers map of the Skiroc2cms, which is shown in Figure 6.2. The information of certain channel can be easily achieved with this map. However, to translate the bits word to readable data. An additional step is needed. Since FPGAs stored the data in gray mode, a gray to binary conversion is needed before analyzing the data from RPI.
For multiple module data taking, the data mapping remains the same. However, the data flow from the master FPGA to the RPI is different. In the test beam the experts have developed another data acquisition system to deal with the multi-module case.
6.2.2 Skiroc2cms CHIP configuration
Users can write different configuration to the CHIP before acquisition. Based on the purpose, Skiroc2cms supports different kinds of functionality in an 384 bit configuration.
The function of each bit is listed in Table 6.1.
Figure 6.2: Skiroc2cms memory map
The HA and HT is a flag to represent the TOT or TOA is fired (Passing the threshold) or not.
Num fuction name bits posi-tion
default comments
1 EN PA 1 1 Enable preampliers
2 PP: PA 2 0 DisablePreAmp power pulsing mode: force on 3 GC: PA
Polar-ity
3 1 Preamplifier polarity: negative = 0 , positive
= 1 4 GC: Capacitor
PA Fdbck
4∼9 8(001000) Preamplifier feedback capacitances: value * 62.5fF
5 GC: Resistor PA Fdbck
10-17 2(00000010) Preamplifier feedback resistors: value*10kohm
6 EN SS G1 18 1 Enable Slow Shaper Low Gain
7 PP: SS G1 19 0 Disable Low Gain power pulsing mode: force on
8 GC: Time
Constant LG Shaper
20-23 8(1000) Low Gain shaping time: value * 5ns
9 EN SS G10 24 1 Enable Slow Shaper High Gain
10 PP: SS G10 25 0 Disable High Gain power pulsing mode: force on
11 GC: Time
Constant HG Shaper
26-29 8(1000) High Gain shaping time: value * 5ns
12 EN Fast shaper 30 1 Enable fast shaper
13 PP: Fast shaper 31 1 Disable fast shaper power pulsing mode (force ON)
13 GC: Time
Constant fast Shaper
32-34 2(010) Fast shaper shaping time: value * 0.625ns
14 EN Discri TOT 35 1 Enable TOT Discriminator
15 PP:
Dis-cri TOT
36 0 Disable TOT Discriminator power pulsing mode (force ON)
16 EN Ramp TOT 37 1 Enable TOT Ramp
17 PP:
Ramp TOT
38 0 Disable TOT Ramp power pulsing mode (force ON)
18 GC: EN Ramp-TOT Fast
39 1 Enable TOT Fast Ramp
19 GC: EN Ramp-TOT Slow
40 1 Enable TOT Slow Ramp
20 EN Discri TOA 41 1 Enable TOA Discriminator Table 6.1: Skiroc2cms configuration part 1
Num fuction name bits
42 0 Disable TOA Discriminator power pulsing mode (force ON)
22 GC: Discrim-inator TOA Polarity
43 0 Discriminator TOA polarity
23 EN Ramp TOA 44 1 Enable TOA Ramp
24 PP:
Ramp TOA
45 0 Disable TOA Ramp power pulsing mode (force ON)
25 TM: Trigger TOA Enable
46-109 64*1 Enable Trigger TOA (channel 0 to 63) 26 TM: Trigger
TOT Enable
110-173
64*1 Enable Trigger TOT (channel 0 to 63) 27 PA: PreAmp
Enabled
174-237
64*1 Enable PreAmp (channel 0 to 63) 28 PA: Ctest
En-abled
238-301
64*0 Enable Ctest for injection runs (channel 0 to 63)
29 PP: Bandgap 302 0 Disable Bandgap operational transconduc-tance amplifier(OTA)0 power pulsing mode (force ON)
30 EN Bandgap 303 1 Enable Bandgap OTA
31 GC: Leakage
311 0 Disable 10-bit DAC1 power pulsing mode (force ON)
313 0 Disable 10-bit DAC2 power pulsing mode (force ON)
37 GC:
DAC1 TOT
314-323
255(0FF) 10-bit DAC (From MSB to LSB) for Trigger TOT Threshold
38 GC:
DAC2 TOA
324-333
255(0FF) 10-bit DAC (From MSB to LSB) for Trigger TOA Threshold
39 EN SCA 334 1 Enable SCA
40 PP: SCA 335 0 Disable SCA power pulsing mode (force ON) 41 EC: Sel ADC
Test
336 0 Select ADC Test input as analogue data to convert
42 EN ADC Discri 337 1 Enable ADC Discriminator
43 PP: ADC Discri 338 0 Disable ADC Discriminator power pulsing mode (force ON)
Table 6.2: Skiroc2cms configuration part 2
Num fuction name bits po-sition
default comments 44 EN Output
OTAq
339 1 Enable Hi-Z Output OTA
45 PP: Output OTAq
340 0 Disable Hi-Z Output OTA power pulsing mode (force ON)
46 EN Probe OTA 341 1 Enable Probe OTA
47 PP: Probe OTA 342 0 Disable Probe OTA power pulsing mode (force ON)
48 GC: AutoOFF OTAq
343 1 AutoOFF OTAq (force ON)
49 EN ADC Ramp 344 1 Enable ADC Ramp
50 PP: ADC Ramp 345 0 Disable ADC Ramp power pulsing mode (force ON)
51 EC: Sel Star-tRampADC Ext
346 0 Select External ADC Ramp commands (for ADC Ramp caracterisation), 0:use ASIC com-mands, 1: use external command
52 GC:
Comp ADC Ramp
347 0 Enable ADC Ramp switch injected charge compensation
349 0 Gain selection (Internal selection [DigitalRead-Out] = 0 , External (by StartReadOut2) [Ana-logue ReadOut] = 1)
59 GC: Chip ID 354-361 255(FF) Chip ID (from LSB to MSB) 60 EC: EN NOR64
TOA
362 1 Enable weak Open Collector Trigger TOA Out signal (1 Trig Out TOA Enabled)
61 EC: EN NOR64 TOT
363 1 Enable weak Open Collector Trigger TOT Out signal (1 Trig Out TOT Enabled)
62 EC:
End ReadOut
364 1 Enable End ReadOut1 = 1 or End ReadOut2
= 0 63 EC:
Start ReadOut
365 1 Select Start ReadOut1 = 1 or Start ReadOut2
= 0
64 EC: ChipSat 366 1 Enable Opened collector ChipSat signal Table 6.3: Skiroc2cms configuration part 3
Num fuction name bits
367 1 Enable Opened collector TransmitOn2 signal 66 EC:
Transmi-tOn1
368 1 Enable Opened collector TransmitOn1 signal
67 NC
369-370
00 68 PP: LVDS
Roll-Clk receiver
371 0 Disable LVDS RollClk receiver power pulsing mode (force ON)
69 EN LVDS Roll-Clk receiver
372 1 Enable LVDS RollClk receiver
70 PP: LVDS
40M Clk re-ceiver
373 0 Disable LVDS 40MHz Clk receiver power puls-ing mode (force ON)
71 EN LVDS 40M Clk re-ceiver
374 1 Enable LVDS 40MHz Clk receiver
72 PP: LVDS
ValEvt receiver
375 0 Disable LVDS ValEvt receiver power pulsing mode (force ON)
73 EN LVDS ValEvt receiver
376 1 Enable LVDS ValEvt receiver
74 PP: LVDS
TrigExt re-ceiver
377 0 Disable LVDS TrigExt receiver power pulsing mode (force ON)
75 EN LVDS TrigExt re-ceiver
378 1 Enable LVDS TrigExt receiver
76 PP: LVDS
RazChn re-ceiver
379 0 Disable LVDS RazChn receiver power pulsing mode (force ON)
77 EN LVDS RazChn re-ceiver
380 1 Enable LVDS RazChn receiver
78 EN LVDS Data Transmitter
381 1 Enable LVDS Data Tx
79 PP: LVDS Data Transmitter
382 0 Disable LVDS Data Tx power pulsing mode (force ON)
Table 6.4: Skiroc2cms configuration part 4
6.2.3 Skiroc2cms readout chain and DAQ
The DAQ system for the Skiroc2cms is comprised of several components, which can be easily separated into the timing system and the readout system. The main task for the timing system is to generate the 25 ns clock and distribute the time stamps to all the readout boards, which controls the data taking of the HGCAL modules. Once the timing system received the trigger signal, all the detectors stop the acquisition process and start to readout and store the data simultaneously.
The readout system consists of several parts, here only the HGCAL readout is dis-cussed. The on-detector part of the readout system has 2 units, the Skiroc2cms ASICs and the FPGA. After collection the data from Skiroc2cms, the on-board FPGA first send the data via the HDMI connection between the module and the interposer, which is the starting point of the off-detector readout. The interposer can send the data via the HDMI to a hardware unit called ORM on the readout boards. There are 8 ORMs on a single readout board, each can handle the data transfer from a single module. On top of each readout board, there is a special ORM (the master ORM) which have the right to com-municate with the raspberry pi 3 (RPI3), which is an unit that can perform the function of the CPU. The master ORM can check the data integrity with the storage devices and it can execute the readout and reset command in all the other ORMs. Figure 6.3 shows the concept of the readout chain in 2017/2018 test beams.
Figure 6.3: Skiroc2cms DAQ, plot from Dave Barney.