SONOS devices with trapped charges in the nitride layer have received much more attention, since SONOS non-volatile-memory devices are inherently free from drain to floating-gate coupling and are able to show a 2-bit/cell storage scheme that utilizes different physical locations to store the injected charges. In this thesis we proposed a new scheme for electron injection (FBEI). Comparing to PASHEI, FBEI has similar behaviors since they are pulse number dependence. Moreover, FBEI and CHEI are very promising since they make the device be able to operate as a 2-bit/cell, due to a large number of charges stored in the specific regime of a cell.
First, we used the I-V measurement with different temperature to observe the Vt
shift, both forward read (FR) and reverse read (RR), after CHEI and FBEI writing.
FBEI shows better window between the difference of FR and RR than CHEI, and the bigger window is still unchanged after 850C during the reading process. By using FVb CP method and FVt CP method, we can extract the VT profile, in which it reveals that most of the charge distributions are close to the drain for FBEI and CHEI. However, the stored charge after FBEI writing shows more concentrated near the drain side than CHEI. Because of this characteristic, it proves and explains again why the window of FBEI is larger than that of CHEI. Moreover, from the method as above, we can obtain the injection direction for both FBEI and CHEI during programming.
Then, we utilized a three-level charge pumping to recognize the programming mechanism. After the measurement, we made an inference of the programming
injected by CHEI will tunnel through the bottom oxide and bump into the nitride as lucky electron model which will cause more damage than FBEI. Therefore, FBEI has better reliability than CHEI does.
Furthermore, based on the experimental results, it was found that FBEI might become a new candidate for 2-bit operation. Thus, we also made the study on 2-bit operation for FBEI comparing with CHEI, with a specific configuration with both source and drain tied together to erase by BBHH (Band-to Band induced Hot Hole), which is utilized to neutralize the stored electrons. The transient characteristic of the second bit shows that we can obtain faster programming speed by FBEI than CHEI.
Even though the first bit is programmed by CHEI, programming FBEI on the second bit can still make it faster than CHEI on the second bit. Finally, we can receive a better endurance for FBEI after 104 P/E cycle and data retention (~1V for program and erase state) for 10 years.
References
[1] M. H. White, D.A. Adams, and J. Bu, “On the go with SONOS,” Circuits and Devices Magazine, IEEE , Vol. 16, No. 4, pp. 22-31, July 2000.
[2] W. J. Tsai, C. C. Yeh, N. K. Zous, C. C. Liu, S. K. Cho, T. W. S. Pan, and C. Y. Lu,
“Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell,” IEEE Trans. on Electron Devices, Vol. 51, no. 3, Mar. 2004.
[3] B. Y. Choi, B. G. Park, J. D. Lee, H. Shin, Y. K. Lee, K. H. Bai, D. D. Kim, D. W.
Kim, C. H. Lee, and D. Park, “Reliable 2-bit/cell NVM technology using twin SONOS memory transistor,” Electronics Letters. Vol. 41 no. 19, 15th Sep. 2005.
[4] M. K. Cho and D. M. Kim, “High performance SONOS memory cells free of drain turn-on and over-erase: Compatibility issue with current Flash technology,” IEEE Electron Device Lett., vol. 21, pp. 399-401, Oct. 2000.
[5] T. Y. Chan, J. Chen, P.K. Ko, and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” in IEDM Tech. Dig., pp. 718-721, 1987.
[6] T. Y. Chan, K. K. Young, and C. Hu “A true single-transistor oxide-nitride-oxide EEPROM device,” IEEE Electron Device Lett., vol. EDL-8, pp. 93-95, 1987.
[7] S. H. Gu and T. Wang, “Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique,” IEEE Trans. on Electron Devices, vol. 53, no. 1, Jan. 2006.
[8] C. C. Yeh, W. J. Tsai, M. I. Liu, T. C. Lu, S. K. Cho, C. J. Lin, T. Wang, S. Pan, and C. Y. Lu, “PHINES: a novel low power program/erase, small pitch, 2-bit per cell Flash memory,” in IEDM Tech. Dig., pp. 931-934, 2002.
[9] M. S. Liang and T. C. Lee, “A hot-hole erasable memory cell,” IEEE Electron Device Lett., Vol. 7, no. 8, pp. 465-467, 1986.
[10] C. Chen and T. P. Ma, “Direct lateral profiling of hot-carrier-induced oxide charge and interface traps in thin gate MOSFET's,” IEEE Trans. on Electron Devices, Vol. 45, no. 2,pp. 512- 520, 1998.
[12] W. Chen, A. Balasinski, and T. P. Ma, “Lateral profiling of oxide charge and interface traps near MOSFET junctions,” IEEE Trans. on Electron Devices, Vol.
40, no. 1, pp. 187-196, 1993.
[13] C. Chen and T. P. Ma, “Direct lateral profiling of both interface traps and oxide charge in thin gate MOSFET devices,” in Symp. on VLSI Tech Dig., pp. 230-231, 1996.
[14] A. M. Martirosian and T. P. Ma, “Improved charge-pumping method for lateral profiling of interface traps and oxide charge in MOSFET devices,” in IEDM Tech. Dig. pp. 93-96. 1999.
[15] C. Y. Lu and K. S. Chang-Liao, “Minimized constrains for lateral profiling of hot-carrier-induced oxide charge and interface traps in MOSFETs,” IEEE Electron Device Lett., Vol. 25, no. 2, pp. 98-100, 2004.
[16] H. Pang, L. Pan, L. Sun, Y. Zeng, Z. Zhang, and J. Zhu, “A new method based on charge pumping technique to extract the lateral profiles of localized charge trapping in nitride,” ESSDERC, 2005.
[17] L. Sun, L. Pan, H. Pang, U. Zeng; Z. Zhang, John Chen, and J. Zhu,
“Characteristics of band-to-band tunnel hot hole injection for erasing operation in charge-trapping memory,” Jpn. J. Appl. Phys., Vol. 45, No. 4B, 2006.
[18] M. Rosmeulen et al., “Characterization of the spatial charge distribution in local charge-trapping memory devices using the charge-pumping technique,”
Solid-State Electr., vol. 48, pp. 1525-1530, 2004.
[19] J. S. Sim, “Observation of the lateral redistribution of locally trapped charge in SONOS memory cells,” SMDL Annual Teprot 2003.
[20] L. Zhizheng and T. P. Ma, “A new programming technique for flash memory devices,” in Symp. on VLSI Tech., pp. 195-198, 1999.
[21] L. Zhizheng and T. P. Ma, “A low voltage erase technique for DINOR flash memory devices,” in Symp. on VLSI Tech. Dig., pp. 17-18, 1999.
[22] N. Tsuji, N. Ajika, K. Yuzuriha, Y. Kunori, M. Hatanaka, and H. Miyoshi, “New erase scheme for DINOR flash memory enhancing erase/write cycling endurance characteristics,” in IEDM Tech. Dig., pp. 53-56, 1994.
[23] S. Haddad, V. H. Chan, H. Fang, Y. Tang, M. Ramsbey, A. Wang, S. Yu, C.
Chang, and J. Lien, “New erase scheme suitable for low power flash memory application,” in Symp. on VLSI Tech. Dig., pp. 52-53, 1996.
[24] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K.
Sugahara, N. Ajika, and S. Satoh, “Device characteristics of 0.35 µm P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming,” IEEE Trans. on Electron Devices, Vol. 46, no. 9, pp.
1866-1871, 1999.
[25] M. Y. Liu, Y. W. Chang; N. K. Zous, I. Yang, and T. C. Lu et al., “Temperature effect on read current in a two-bit nitride based trapping storage flash EEPROM cell,” IEEE Electron Device Letters, Vol. 25, no. 7, July 2004.
[26] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. H. Wang; S. Pan, C.
Y. Lu, and S. H. Gu, “Data retention behavior of a SONOS type two-bit storage Flash memory cell,” in IEDM Tech. Dig., pp.32.6.1-32.6.4, 2001.
[27] C. C. Yeh, W. J. Tsai, T. C. Lu, S. K. Cho, T. Wang, S. Pan, and C. Y. Lu, “A modified read scheme to improve read disturb and second bit effect in a scaled MXVAND Flash memory cell,” in Proc. Non-Volatile Semiconductor Memory Workshop, pp.44-45, 2003.
[28] F. S. Shoucair, ” Scaling, subthreshold, and leakage current matching characteristics in high-temperature (25°C-250°C) VLSI CMOS devices,” IEEE Trans. COMP., Hybirds, Manufact. Technol., Vol. 12, pp. 780-788, Dec. 1989.
[29] F. S. Shoucair, “Design considerations in high temperature analog COMS integrated circuits,” IEEE Trans. COMP., Hybirds, Manufact. Technol., Vol.
CHMT-9, pp. 242-251, Sept. 1986.
[30] J. D. Bude et al., "Secondary electron Flash - a high performance, low power Flash technology for 0.35 pm and below," in IEDM Tech. Dig., pp. 279-282.
1997.
[31] W. L. Tseng, “A new charge pumping method of measuring Si-SiO2 interface states,” J. Appl. Phys., Vol. 62, p.591, July 1987.
[32] N. S. Saks and M. G.. Ancona, “Determination of interface trap capture cross sections using three-level charge pumping,” IEEE Electron Device Letters, Vol.
11, no. 8, Aug. 1990.
[33] M. J. Kivi and S. Taylor, “Assessment of nMOSFET degradation using three level charge pumping,” in International Conference on Microelectronics, Vol. 1,
[34] T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N.
Ajika, M. Hatanaka, and H. Miyoshi, ” Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell,” in IEDM Tech.Dig., pp. 279-282, 1995.
[35] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K.
Sugahara, N. Ajika, and S. Satoh, “Device characteristics of 0.35 µm P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming,” IEEE Trans. on Electron Devices, Vol. 46, no 9, pp.
1866-1871, 1999.