In this thesis, the effects of capping a PECVD SiN layer over the gate of NMOSFETs on the device characteristics and hot-carrier degradation are investigated.
Several important phenomena are observed and summarized as follows.
The channel strain induced by the SiN capping layer over the gate enhances the device performance greatly by boosting the drive current. As SiN capping layers increases, the device performance becomes better due to the increase of tensile stress exerted on the channel. For example, in the device with the thickest SiN capping layer (SiN-3kÅ) explored in this study, drain current enhancement ratio of more than 17%
and the transconductance enhancement ratio of more than 29% are achieved at a channel length of 0.4μm. The poly depletion effect, a phenomenon that we encountered in previous study on devices capped with LPCVD SiN, is eliminated in this work with the PECVD process. This is attributed to the negligible thermal budget of the PECVD deposition so that the activated carriers concentration in the poly-Si gate is not affected.
However, the band-gap narrowing effect caused by channel strain will result in worsened threshold voltage roll-off characteristics.
The hot carrier degradation is greatly affected by the channel strain level of the SiN capped devices. With the increasing channel strain associated with increasing SiN thickness, the accompanying band-gap narrowing and the increasing carrier mobility will tend to worsen the hot carrier reliability in the SiN capped devices. The interface states caused by the breaking of Si-H bonds at the oxide/channel interface by hot carriers also lead to performance degradation.
In this work, tensile stress could be enhanced by increasing SiN thickness and
therefore device performance could be boosted, especially for short channel devices.
However, the hot carrier reliability was also degraded owing to the increase in mobility and the use of hydrogen-containing precursors during the deposition of SiN capping layers. How to reduce the hydrogen content in the SiN without compromising the tensile stress is essential to the implementation of uniaxial-strain NMOS devices.
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Fig.1.1 Schematic illustration of 3D process-induced strain components [25].
Schematic view of 3D process-induced strain components.
Impact of 3D Strain Effects on CMOS Performance.
*Strain change=Increased tensile of decreased compressive strain.
Fig.1.2 Simple schematic of conduction and valence band structures with and without strain [35].
Fig.1.3 Schematic diagram of the energy sub-bands without strain and with bi-axial strain in an MOS inversion layer [27].
Fig.1.4 Schematic diagram of the valence bands E vs. k in uni-axially tensile strain and bi-axially tensile strain Si layers [29].