Semiconductor flash memory device technology will continue to play an important role in the electronics industry, although its development has been facing a lot of challenges. Conventional FG structure suffers from serious coupling issues that degrade the device characteristics and may eventually limit further device scaling. It thus faces fierce competition from a number of new types of devices, including the SONOS.
In this thesis, we fabricate, characterize, and compare the characteristics of FG and SONOS flash non-volatile memory device using a conventional process with LOCOS isolation. Fundamental electrical characteristics, program/erase (P/E) speed, and the associated reliability were investigated. Several important phenomena were observed and summarized as follows.
First, we found that the gate coupling effect indeed hinders the operation of FG devices. Aggravated short-channel effect (SCE) is observed for FG devices scaling because of the gate-to-drain parasitical coupling effect. Such situation could be effectively relaxed with the SONOS devices, owing to the use of an ultra-thin charge storage layer which could help reduce the height of the gate structure.
Secondly, although the SONOS devices exhibit slower programmed speed over the FG ones, it can be improved by using a thinner tunneling oxide. It also reveals that good subthreshold characteristics could be retained for these devices after write/erase cycles.
Thirdly, interface trap generation is mainly responsible for the threshold voltage shift of SONOS devices after a large number of P/E cycles. Such effect, however, may
tunnel oxide is identified as the major mechanism for FG devices, causing a shrinkage of Vt window with increasing number of P/E cycles.
New materials and novel device structure are always indispensable for flash memory scaling and device performance improvement. From the results obtained in this work, it is confirmed that discrete trap-based flash memory is more scalable than FG memory device. Besides, the fabrication of SONOS devices is compatible with current CMOS processing and is thus a suitable candidate for embedded memory applications. In order to achieve better chip performance and low cost, however, more efforts are required to further optimize the device performance, especially the reduction of P/E speed and better reliability.
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Tables
Table 3.1 Performance and operation window between the FG and the SONOS memory devices.
Table 3.2 Endurance operation conditions in the FG and the SONOS memory devices.
Figures
..
Fig 1.1 Scaling trend for flash memory device development [13]
Fig 1.2 Diagrams illustrating physical structures of floating-gate and discrete trapping (SONOS) devices [7]
(a) (b)
Fig 2.1 Flash memory device process flows: (a) conventional floating gate flash and (b) silicon-oxide-nitride-oxide-silicon (SONOS) stacked gate flash.
(a) (b)
Fig 2.2 Flash memory device structure (a) Cross-sectional view and (b) Layout.
(a) (b)
Fig 2.3 Cross-section view of flash memory devices with (a) Floating gate and (b) SONOS stacked gate.
Fig 2.4 Experimental setup for basic charge pumping measurements.
Fig 2.5 Detailed schematic for charge pumping measurement setup.
Fig 2.6 Principles of Icp current measurements.
Fig 2.7 Schematic illustration of charge pumping measurements with fixed amplitude.
Fig 3.1 ID–VG Characteristics of N-channel FG and the SONOS memory devices. Channel length/width = 0.65μm /0.5μm.
Fig 3.2 ID–VD Characteristics of N channel FG and the SONOS memory devices. Channel length/width = 0.65μm /0.5μm.
(a)
(b)
Fig 3.3 Channel-initiated secondary electron (CHISEL) programming mechanism for n-channel SONOS memory device. (a) Programming conditions and related events inside the substrate. (b) Band gap diagram for the programming.
(a)
(b)
Fig 3.4 Hot holes injection (HHI) erasing characteristics of N channel SONOS memory device. (a) Erasing conditions and mechanisms. (b) Erasing band gap diagram.
(a)
(b)
Fig 3.5 VD operation range of programming. (a) CHISEL programming for SONOS devices. (b) CHEI programming for FG devices..
Fig 3.6 CHEI (VB=0) and CHISEL (VB<0) programming efficiency (IG/ ID) of carries injection for the SONOS memory devices with channel
length/width = 0.65μm /0.5μm.
(a)
(b)
Fig 3.7 Programming characteristics of the SONOS memory devices. (a)
Programming speed performance for different substrate bias (b) ID–VG
curves in different CHISEL programming time with VB=-4V.
(a)
(b)
Fig 3.8 Hot hole injection (HHI) erasing characteristics of the SONOS memory device. (a) Threshold voltage shift window and erasing speed. (b) ID–VG
curves under different HHI erase time with VB=5V.
Fig 3.9 Threshold voltage window of the SONOS memory device between CHISEL programming and HHI erasing.
Fig 3.10 Subthreshold characteristics of FG and SONOS memory devices at different stage of operations.
Fig 3.11 ID–VG characteristics of forward read (VD =1.5V) after programming and erasing in the floating gate and the SONOS memory devices.
Fig 3.12 Threshold voltage of programmed and erased states as a function of VD for the two types of devices.
(a)
(b)
Fig 3.13 Schematic of parasitic carrier injection mechanisms under drain disturb on programmed cells. (a) Drain disturb in flash array circuit. Cell #1 is programmed and cell #2 is not programmed but sharing the same bitline (b) Hole BBT tunneling current may incur in the drain overlap region of the Cell #2 devices [32].
(a)
(b)
Fig 3.14 VD Stress versus threshold voltage shift. (a) The floating gate devices.
(b) The SONOS devices.
(a)
(b)
(c)
Fig 3.15 Data retention characteristics under elevated temperature stress at 50
oC, 85 oC and 125 oC. (a) CHEI program for FG devices. (b) CHISEL program for SONOS devices. (c) CHEI program for SONOS devices
(a)
(b)
Fig 3.16 (a) The charge loss paths and the various leakage current components in an SONOS device [35]. (b) Charge loss performed at difference thermal stress for the SONOS memory device with channel length/width = 0.65μm /0.5μm.
(a)
(b)
Fig 3.17 Endurance characteristics after program/erase (P/E) cycling stress. (a) The FG device. (b) The SONOS device.
(a)
(b)
Fig 3.18 Subthreshold characteristics after 1 and 5000 times P/E cycles.
Channel length/width = 0.65μm /0.5μm. (a) The FG device. (b) The SONOS device.
(a)
(b)
Fig 3.19 Subthreshold characteristics and transconductances of the FG
memory device with length/width = 0.65μm /0.5μm. (a) Erasing and (b) programming operations.
(a)
(b)
Fig 3.20 Subthreshold characteristics and transconductances of an n-channel SONOS memory device with length/width = 0.65μm /0.5μm. (a) Erasing and (b) programming operations.
(a)
(b)
Fig 3.21 Degradation of (a) Subthreshold swing and (b) transconductance of the FG and the SONOS memory devices as a function of P/E cycles.
(a)
(b)
Fig 3.22 Increase in charge pumping current (UIcp) after 1000 and 5000 P/E cycles for an FG device. The measurements were performed under fixed amplitude of 1.5V and frequency of 1MHz. (a) Erasing state. (b) Programming state.
(a)
(b)
Fig 3.23 Increase in charge pumping current (UIcp) after 1000 and 5000 P/E cycles for an SONOS device. The measurements were performed under fixed amplitude of 1.5V and frequency of 1MHz. (a) Erasing states. (b) Programming states.
(a)
(b)
Fig 3.24 Interface state generation after P/E cycling of both flash memory devices with channel length/width = 0.65μm /0.5μm. (a) The FG device (b) The SONOS device.