T HESIS O RGANIZATION

The rest of this thesis is organized as follows. At first, the basic knowledge of the embedded silicon ( eCrystal ) [35] oscillator will be described in Chapter 2. Then, we propose an all digital phase locked loop for eCrystal calibration designed in Chapter 3. In Chapter 4, we present an all digital pulse-width control loop with adjustable duty cycle. Finally, Chapter 5 summarizes our work and discusses some design topics in the future.

Chapter 2

THE BASICS OF THE EMBEDDED SILICON OSCILLATOR

Quartz crystal frequency references have long been recognized as the most cost effective method of maintaining frequency accuracy in signals for wireless communications. In consumer communications products, such as cellular telephones and televisions, the cost of the crystal routinely accounts for no more than of 1% of the total material cost of the unit [5].

To meet high integration, low power consumption and low cost for computers of consumers and communication products, an embedded silicon oscillator (eCrystal) [35] is desired to replace existing crystal and external components. In this chapter, the basic knowledge of the embedded silicon oscillator is briefly described.

2.1 Introduction to Embedded Silicon Oscillator

FIG. 1 shows the concept of eCrystal oscillator to replace the external components. By the use of eCrystal oscillator, the external and existing crystal can be eliminated and integrated into a single

function chip. A remote reference tone is used to calibrate the initial frequency offset of clock generator which illustrates in section 3.2. FIG. 2 shows the accuracy of eCrystal system for possible different applications after calibrated.

FIG. 1. The concept of eCrystal oscillator to replace the external components

FIG. 2. The accuracy of eCrystal system for possible different applications

Several approaches have been proposed to replace the quartz crystal, including Micro Electro Mechanical Systems (MEMS) oscillator, LC tank oscillator and Ring oscillator. Unfortunately,

there are many disadvantages in each approach. MEMS [6-7] oscillators have certain disadvantages which include limited power-handling capability, and special process and package. LC tank oscillator [8] is suitable for low-noise radio frequency synthesis, but the drawback is high power consumption, large area on the top layer metal of a die, and poor portability. Ring oscillator [9]

seems to a better solution to chip integration power budget and area, but the disadvantage is the operational amplifiers in voltage regulator and comparator consume large power. Moreover, when the CMOS technology scaling to the next advanced generation, the violent frequency variation rate of ring oscillator is about 60 ~ 70% under the worst case PVT corners in 90nm process. TABLE 1 shows the comparison of state of the arts.

TABLE 1: The Comparison of each Proposed.

2.2 Design Challenge

The key challenge of an on-chip oscillator design is to maintain the stability of frequency due to process, voltage, and temperature (PVT) variations. The bandgap regulator techniques [9-10] are applied for suppressing the supply voltage variation. The process and temperature variations are sensed or compensated by carefully refining the transistor configurations. The current limiting technique [11] is proposed to compensate temperature variation. Nevertheless, these methods are not easily portable when fabrication process migrates toward deep sub-micron (DSM) scale.

Moreover, there is a design barrier when the conventional bandgap regulator operates under 1.2-V supply voltage [12], whereas the all-digital design approach is power efficient, portable with process migrations, and easily to be adopted in low supply voltage.

0.9 0.95 1 1.05 1.1 1.15

FIG. 3. Delay spread of a delay line composed of 100 buffers connected in a series under PVT variations.

In CMOS process, gate delay is strongly affected by PVT variations and it can be modeled as a function of PVT described as D(P,V,T). FIG. 3 shows the delay spread of a delay line composed of 100 buffers connected in a series of a 90-nm CMOS process. The delay varies widely from 2.8ns to 7.5ns with different supply voltage and temperature across process corners of SLOW, TYPICAL, and FAST which are provided by foundry. If the delay line is applied in a free running ring oscillator, PVT variations make the oscillation frequency unstable. Even if the process variation is calibrated in a post process testing, the frequency variation is still high and unpredictable due to the unknown supply voltage and operation temperature.

2.3 Architecture

A simple architecture is shown in FIG. 4. It is composed of three blocks, including delay ration estimator, mapper and digitally controlled oscillator. The delay ratio estimator calculates the delay ratio of two different delay cells (DVAR (P.V.T)/ DREF (P.V.T)). The delay ratio of these two delay cells is aimed to estimate the delay of the reference delay cell. To strengthen the difference of the delay behavior to PVT conditions in these two delay cells, we adopt NAND gate as the compared delay cell and BUFFER gate as the reference delay cell. Sweeping the PVT conditions of three process corners with voltage range from 0.9V to 1.1V and temperature range from 0℃ to 75℃, the delay of the reference delay cell to the delay ratio is plotted in FIG. 6. The curve of the reference delay can be approximated by , which is a second order function of the delay ratio R(P,V,T), that is ,where a, b, and c are process dependent parameters (PDPs). Three process corners are fitted by three sets of PDPs. The PDPs can be obtained by a post-process testing with at least three voltage and temperature conditions in the curve. The delay of the reference delay cell is estimated. The DCO is based on a ring oscillator with

(

adjustable hysteresis delay cell (HDC) length in the delay line. The desired frequency, , as

FIG. 4. System Architecture of the eCrystal oscillator.

0.9 0.92 0.94 0.96 0.98 1 1.02

FIG. 5. Relation between the delay of the reference delay cell and the delay ratio.

From Equation. 1, the extra combinational delay can be neglected, because the variation is far less than the main delay line in the delay path. We can fix the target frequency, , and f_des

according to the locked codeword representing the target frequency, to solve a, b, and c parameters.

These behave like a phase lock loop (PLL) which controls the DCO and compare the CLK frequency to the external reference frequency. So, we propose an all digital phase lock loop (ADPLL) to provide an accurate lock code. The details will be illustrated in chapter 3. According to the delay ratio and process dependent parameters, mapper is able to transfer the control code for calibrating the PVT variations. The DCO receives the digital control code from the mapper and generates the target frequency clock without any external components

The quality of the clock signal which is based on frequency, phase, and duty cycle, undoubtedly influences the system performance. With the advanced technology, many digital clocks not only have low jitter, but also need 50% duty cycle to double the data rate, such as DDR SDRAM. Some special analog-to-digital (ADC) or digital-to analog (DAC) systems [2] need the clock generators with programmable duty cycles. In order to achieve a better performance in the clock system, an all digital pulse width control loop (ADPWCL) design will be further discussed in Chapter 4.

Chapter 3

ALL DIGITAL PLL FOR ECRYSTAL PROCESS CALIBRATION

Phase locked loops (PLLs) are widely used in modern communication systems and high performance microprocessors because of their remarkable versatility. PLLs are used to lock or track input signals in phase and frequency. The digital approach has low design complexity for power minimization, and easy integration in SoC applications. Also, it achieves fast lock times by using all-digital PLLs (ADPLLs). The ADPLLs have better testability, programmability, stability, and portability. Therefore it is suitable to acquire the accurate process dependent parameters (PDPs) for eCrystal calibration.

In this chapter, a process calibration circuit using an all-digital phase locked loop (ADPLL) technique is realized in UMC 1P9M 90nm CMOS process. The proposed ADPLL for eCrystal calibration achieves a capable of calibrating PVT variations. According to the lock code from the proposed ADPLL, the testing machine will calculate the a, b, c parameters and will be recorded into a one-time programming (OTP) or register files. The mapper will combine the delay ratio and pick up PDPs from OTP or register files to calibrate the frequency error without any external components. In section 3.1, we will simply introduce four kinds of PLL applications, and pick item

three (clock generator) which is similar with our system requirement. In section 3.2, we will give an overall system overview and design specification. The details in ADPLL for eCrystal process calibration are illustrated in the following sections.

3.1 Introduction to Phase Locked Loop

The APLL (also know as Linear Phase-Lock Loop (LPLL) is a traditional PLL, which was proposed back in 1930s by French Engineer, H. de Bellescize. The initial ideas started as early as 1919 in the context of synchronization of oscillators. The theory of phase-locked loop was based on the theory of feedback amplifiers.

A PLL is a circuit which causes a particular system to track with another one. More precisely, it is a feedback loop which synchronizes an output signal with a reference or input clock in frequency as well as in phase. In the locked stated, the phase error between the oscillator’s output and the reference clock is either zero or an arbitrary constant.

Due to the rapid development of integrated circuit (IC’s) since 1970’s, PLLs are widely used in modern signal processing and communication systems, and it is expected that PLL will contribute to improvement in performance and reliability of future communication systems. The main applications of PLL are as follows:

1. Clock recovery: Some data streams, especially high-speed serial data streams, (such as the raw stream of data from the magnetic head of a disk drive) are sent without an accompanying clock.

The receiver generates a clock from an approximate frequency reference, and then phase-aligns to

the transitions in the data stream with a PLL. In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLL's oscillator.

2. Deskewing: If a clock is sent in parallel with data, that clock can be used to sample the data.

Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a de-skew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock.

3. Clock generation: Most electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertzes and the reference crystal is just tens or hundreds of megahertz.

4. Spread spectrum: All electronic systems emit some unwanted radio frequency energy.

Various regulatory agencies (such as the FCC in the United States) put limits on this emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spread-spectrum PLL to reduce interference with high-Q receivers by spreading the energy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen by FM receivers which have a bandwidth of tens of kilohertz.

3.2 System Overview

The embedded silicon (eCrystal) communication system is composed of a master node and a slave node, which is compatible in most of the current communication systems. The slave node in the eCrystal communication system can eliminate the use of an external quartz crystal oscillator and replace by an eCrystal oscillator. The eCrystal oscillator applies a standard CMOS process and can be directly integrated into a single chip. A remote reference tone is used to calibrate the initial frequency offset of clock generator As a result, the cost of board level integration and external power consumption are reduced. FIG. 7 shows a simple eCrystal communication system.

FIG. 6. A simple eCrystal communication system

FIG. 7. The proposed all-digital phase locked loop for process calibration

The slave node baseband of the embedded silicon (eCrystal) oscillator communication system with proposed all-digital phase locked loop for eCrystal process calibration is depicted at red sub-area in FIG. 8. The slave node baseband contains an eCrystal including delay ratio estimator, mapper, and digitally control oscillator (DCO) and PDP. The eCrystal is designed to provide 5MHz frequency for the baseband clock and radio frequency carrier synthesis.

After a chip is fabricated, the standard logical or functional test will be executed on a testing machine. Meanwhile, the accurate reference frequency (Flocal_ref) is available, and the testing cycle is adequate for the local reference tracking. The local reference tracker behaves like a phase lock loop (PLL) which controls the DCO and compare the CLK frequency to the external reference frequency. After the frequency is locked, the Locked Code is provided along with the Ratio from delay ratio estimator. Besides, the chip will be tested under different operation corners. Collecting

the different corner Locked Code and Ratio data, we are able to calculate the process dependent parameters (PDPs) which will be recorded into a one-time programming (OTP) device or register files.

The master node of a communication system provides a reference carrier frequency in the down-link communication for calibration. The received remote reference frequency is then down-mixed with the local oscillation signal which is synthesized from the eCrystal oscillator clock.

If the local frequency is exact the same as the remote reference frequency, the residual frequency error (Ferror) will be zero. The remote reference tracker needs 2ps resolution of DCO. Otherwise, the residual frequency error fed to the slave node baseband is tracked by the remote reference tracker, and it will adjust the DCO until the frequency error shrinks to a tolerable value which baseband signal processor can handle.

The remote reference tracker is on the frequency calibration behavior combined with a 420-430MHz band FSK module. The remote frequency tracker is a common system block in both eCrystal FSK solution and eCrystal OFDM-based WiBoC (Wireless & Imaging Business Owners Consortium) solution and can be applied to both designs. The design challenge is to track and calibrate the frequency error within 5% which is quite high in a communication system. By adjusting the DCO, the final calibrated frequency error will be within 0.3%. The calibration time should be small than 10ms to reduce the communication traffic overhead. The baseband signal processor including a synchronizer, channel equalizer, and an Orthogonal Frequency Division Multiplexing (OFDM) modulator and demodulator is developing a synchronizer which can detect the down-link signal and to synchronize through adjusting the DCO. The signal processor can tolerate frequency error up to 0.3% and adjust the DCO frequency to below 20ppm. After synchronization, the up-link communication can transmit data. This block and the remote reference tracker block target on reducing frequency error between a master node and a slave node.

The local reference tracker is to track the reference frequency and provide the locked code under testing procedure. The power and locked time is less critical due to its operating occasion is only once. The proposed design will be illustrated in next section. The design specification of local reference tracker is listed in TABLE 2, including 5MHz reference clock source and 5MHz target output Locked Code with 20ppm frequency error.

TABLE 2: Specification of ADPLL for the eCrystal process calibration.

The DCO adopts the HDC (Hysteresis Delay Cell )-based [16-17][36] delay cell which can achieve an excellent performance on power consumption. However, the most concerned issue on the HDC-based DCO is the linearity under PVT variations. The hysteresis delay cell has a worse PVT variation than a typical delay cell, also it has a non-monotonic phenomenon.

The delay ratio estimator along with a mapper will provide an initial control code for DCO under PVT variations. The design challenge is to estimate the delay ratio within 0.1% and to map the DCO frequency with as little error as possible. If the error is reduced, the calibration effort will be relaxed and the overhead in communication is reduced.

3.3 Architecture

This proposed all-digital phase locked loop for process calibration architecture is shown in FIG. 9. This all-digital phase locked loop (ADPLL) consists of phase frequency detector (PFD), hysteresis delay cell based-digitally controlled oscillator (HDC-DCO), control unit (CU) and digital loop filter (DLF).

FIG. 8. The proposed all-digital phase locked loop for process calibration architecture.

There are two operations in the system; one is used for the embedded silicon oscillator calibration named calibration mode and the other is used for generating the output clock without the reference clock source named operation mode. The difference between the operation mode and the calibration mode is reference clock source. One is for quartz crystal oscillator and the other is for eCrystal without any reference source.

In the operation mode, by using the power gating cell which can be gated the power consumption from PFD, CU and DLF, the output clock is generated at 5MHz by the embedded silicon oscillator which is a small and a highly integrated circuit. In the calibration mode, the output clock is directly connected to the PFD which detects the difference of frequency and phase between

the clock of external quartz crystal and HDC-DCO output. Then, it generates an up (UP) and down (DOWN) signal to indicate CU that adjusts HDC-DCO control codeword to speed up or slow down the output frequency of HDC-DCO, respectively. According to the developed search algorithm [14-15], the whole all-digital PLL operation mechanism is illustrated in FIG. 10.

FIG. 9. All-digital PLL operation mechanism

After the system reset, the CU sets the DCO at the middle of delay path. The initial search step of DCO is n/4, where n is the number of frequencies provided by the DCO. The binary search will pass through the three states to converge the output frequency as close as possible to reference

clock. Each state employs different tuning range and resolution as shown in FIG. 11.

FIG. 10. The tuning range and resolution of each three state

While the PFD detects from lead to lag, the search step is divided by two, and vice versa [14].

Each time when a new DCO code is calculated, the current DCO and PFD control signals will be cleared before the DCO is updated. Clearing DCO signal avoids glitches which result from directly updating DCO codeword. At the same time, clearing PFD signal keeps the coarse-tuning loop from frequency and phase divergence [16].

When the search step becomes to one, ADPLL finishes frequency and phase acquisition. Then ADPLL will become the average state which will search the maximum and minimum DCO code to generate more accuracy average Locked Code. According to polarity, trend and flow signals, the

digital loop filter (DLF) will detect the maximum and minimum DCO codeword with 2^nd fine tuning range during the multi-reference clock cycles, which the output (DCO codeword (max + min) /2) is the average DCO Locked Code. If the lock-counting signal of the controller is inversed by six

digital loop filter (DLF) will detect the maximum and minimum DCO codeword with 2^nd fine tuning range during the multi-reference clock cycles, which the output (DCO codeword (max + min) /2) is the average DCO Locked Code. If the lock-counting signal of the controller is inversed by six