Our method can handle circuits that have two or three kinds of supply voltages, circuits with more than three supply voltages is also processible. If there is only one supply voltage overall the circuit, then our program will run like original B*-Tree simulated annealing method, and will not spend extra runtime to handle voltage island property. We implemented our algorithm in the C++ programming language on a PC with P4-2.4GHz cpu and 440MB memory. We experiment with our ap-proach on MCNC circuit benchmark, and compare with [2], the original B*-Tree with simulated annealing method.
To compare the power routing complexity, and the overhead area due to level converters, we adopt a simple method to estimate the cost of it. Wire connections between two blocks in different islands always need level shifters to change its signal levels, we assume that all level converters are placed on the periphery of voltage islands (the boundary of the two islands), except for the boundary of the chip. The main reasons are that, firstly, we preserve a thin layered unit level converter area on the boundary between two different islands, and it is enough for the required area of all level converters for the wire connections; secondly, the power pins located on the outmost periphery (the boundary of the chip), so we do not place level converters there.
Moreover, although different types of level converters may need different sizes of area to implement, we simply assume all level converters are the same size. Based on above assumptions, we count the boundary length except the outmost side to be the power routing/overhead area cost. Table 4.1 show the experiment results, columns 1 and 2 give the name of the circuit (the number of blocks) and the power tables we use, and the power consumption in column 5 is lowest since we use the lowest available voltages for every block in it, and we compare the power routing/overhead converter area cost from [2], which are normalized to ours.
We experiment our method by testing with different power tables, which are comprised of (supply voltage, power dissipation) pairs. They are randomly assigned in order to simulate the fact that different functional cores may be different in their power density or supply voltage. Pt2 is the power table that contains 2 different supply voltages, while pt3, pt3 1, pt3 2 are power tables contains 3 folds. Figure 4.1 is a feasible placement1 result graph of our voltage island generation method.
Note that even we use pt3 (or pt3 1, pt3 2) to construct voltage island, if the area or wirelength requirement is tight, we may get the placement solution raising the lower voltage blocks to a higher supply voltage to meet the requirement (we may finally get a floorplanning/placement that are only 2 folds of voltage supplies even we use pt3 series power tables to be the power information, an illustration examples are shown in the Figure 4.2). Figure 4.3 is an example of a placement without voltage island generation methodology, it is a scrambled placement even the power consumption is the lowest.
From Table 4.1, we can see that our runtime is about 3 times to an original B*-Tree method. Although our power consumption is a little more than the lowest power listed in column 5 (because we assume they use lowest power), but our routing/level
1A feasible placement in B*-Tree representation with performance constraints is a placement that no any two blocks overlap each other while each block can not be move left or down and requirement of performance constraints is meet.
Table 4.1: The comparison between [2] and our approach on power consumption and power routing cost. The results are obtained from some MCNC benchmarks with different power tables. Area in mm2, dead space(Dead) in%, power consumption(P) in mW and runtime(T) in seconds. C is level converters area and routing cost.
Original B*-Tree [2] Ours
pt3 113.6 4.52 1.181 2.07% 123.2 89
ami33
pt3-1 1.27 8.94%
131.1 4.76 26
1.183 2.23% 136.3 89
pt2 147.1 4.18 36.67 3.34% 151.5 243
pt3 142 5.43 36.68 3.38% 156.2 234
pt3-1 183.1 6.11 36.75 3.52% 196.4 234
ami49
converters cost is about 16.4% - 55.2% compared with [2].
In order to compare our results with [2] and [17] in similar number of voltage islands and especially power routing cost, we come up with a heuristic that adjusts supply voltage of the original B*-Tree results: For a floorplan/placement, we raise firstly the block that is surrounded by the blocks applying the highest voltage (be-cause a block that applies highest voltage means that its voltage can not be changed to other voltage levels) until all the blocks applying highest voltage are connected together to be a island. We fix the blocks that applying highest voltages, then take care of the blocks applying second high voltage, the same method is used until they form a island, too. Voltage islands generation is completed until all voltage level are considered.
Figure 4.4 is an initial floorplan/placement without voltage island generation methodology applying the lowest power, and Figure 4.5 is the placement result after applying the heuristic to raise voltages of some blocks, and 3 - 4 voltage islands with 3 kinds supply voltages is acceptable. Figure 4.6 is an example of raising all lowest voltage to form a two voltage islands floorplan/placement with 2 kinds of supply
Table 4.2: The comparisons between power amount that need to be raised to form a voltage island floorplan/placement. The number of voltage islands and power routing/level converters area cost are nearly the same for both approaches.
Ours Original B*-Tree [2]
Circuit Table Lowest
Power Percentage Power Percentage
pt2 83.7 86.4 3.2% 97.9 16.7%
hp pt3 73.4 78.3 6.7% 91.6 24.8%
pt3 113.6 123.2 8.5% 136.8 20.4%
ami33
pt3-1 131.1 136.3 4% 161.7 23.3%
pt2 147.1 151.5 3% 171.4 16.5%
pt3 142 156.2 10% 169.6 19.4%
pt3-1 183.1 196.4 9.7% 239.6 30.1%
ami49
pt3-2 208 222.9 7.2% 254.3 22.3%
voltages.
The power in column 4, 6 and the percentage in column 5, 7 are the power for nearly the same cost in number of voltage islands and the increased percentage according to the lowest power column 3 of Table 4.2. We can see that at least 10%
- 20% power consumption can be saving by our method, not to mention the good shape of our generated voltage islands.
Table 4.3 show the comparisons of our results with [17] which considers only alignment and performance constraints. Our approach considers performance con-straints and the generation of voltage islands.
Finally, we show Figure 4.7 and 4.8, two placement results that simultaneously consider voltage island generation and performance constraints. Figure 4.7 is a placement example applied tighter constraints, while Figure 4.8 is a looser one.
Table 4.3: Comparisons of the floorplanning/placement results including perfor-mance constraints with [17].
Perf. Constraint Only[17] Ours Circuit Table Perf.
Area Dead P C Area Dead P C
pt3 113.6 4.34 1.18 2.02% 121
ami33
pt3-1 3 1.181 2.2%
131.1 4.93 1.181 2.2% 145.1
pt2 147.1 4.5 36.78 3.64% 156
pt3 142 6.33 36.89 3.93% 154.5
pt3-1 183.1 6.89 36.87 3.86% 200.9
ami49-2
pt3-2
3 36.56 3.1%
208 6.7 36.89 3.93% 221.9
pt2 147.1 4.48 36.8 3.68% 156.8
pt3 142 6.43 36.98 4.14% 149.7
pt3-1 183.1 6.6 37.1 4.46% 215.9
ami49-3
pt3-2
6 36.64 3.3%
208 6.25 37.07 4.38% 223.3 1
0 200 400 600 800 1000 1200 1400 1600 1800
0
Figure 4.1: A feasible placement of circuit ami33 with 3 usable supply voltages.
Dead space=2.07%, power=123.2mW while the lowest power =113.6mW (since we want smaller dead space, we must give away some power).
0 1000 2000 3000 4000 5000 6000 0
1000 2000 3000 4000 5000 6000 7000
Figure 4.2: A feasible placement of circuit ami49 with 3 usable supply voltages power table information, but this placement result only use 2 kinds of supply voltages.
Dead space=3.38%, power=156.2mW while the lowest power =142mW .
0 500 1000 1500
0 500 1000 1500
Figure 4.3: A traditional placement of circuit ami33 without voltage island genera-tion methodology. Dead space=1.47%, and the power routing/level converter area cost=4.77.
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Figure 4.4: An illustration of circuit ami33 without voltage island methodology.
Dead space=2.12%, power=113.6mW .
0 200 400 600 800 1000 1200
0
Figure 4.5: An illustration of circuit ami33 applying heuristic of supply voltage adjusting method for original B*-Tree result in Figure 4.4. We raise some blocks’
supply voltages to reduce some power routing and area overhead due to level con-verters. Power=136.8mW , a 20.4% increase in power consumption compares to the lowest power dissipation.
0 200 400 600 800 1000 1200
Figure 4.6: An example of circuit ami33 from Figure 4.4 raising all the lowest supply voltage and forming two voltage islands finally. Power=146.3mW , a 28.8% increase in power consumption.
Figure 4.7: A feasible placement result with performance constraints consideration.
Circuit ami33 with blocks 5, 6 and 7 under tighter performance constraints. Dead space=2.30%, power=116.9mW while the lowest power =113.6mW .
0 1000 2000 3000 4000 5000 6000 7000 0
1000 2000 3000 4000 5000 6000
7
6 5
Figure 4.8: A feasible placement result with performance constraints consideration.
Circuit ami49 with blocks 5, 6 and 7 under looser performance constraints. Dead space=4.53%, power=146.6mW while the lowest power =142mW .