Coating Aluminum with Thermal Coater

2.7.3 Al sintering at 450℃ in N2 ambient for 30 minutes

Nanowires with two different sizes were fabricated. Wires in group 1 was formed by spacer, and wires in group 2 (test sample) was made through lithography.

The detailed fabrication process flow of group 2 are listed as follows (Figure 2-7).

1. (100) orientation Si wafer 2. Initial cleaning

3. Thermal wet oxidation at 1100℃ to grow 300nm thermal SiO₂ in horizontal furnace.

4. 150 Å α-Si was deposited by LPCVD with SiH₄ gas

5. 500 Å SiGe was deposited by UHVCVD at 550℃ with SiH4 and GeH4

gas

6. Oxidation in various temperature and time 7. Mask#1：Define S/D and channel

8. 500 Å SiGe + 150 Å α-Si wet etching by poly etching solution 9. RCA cleaning

10. 100nm gate dielectric deposition by PECVD at 300℃

11. 200nm poly-Si was deposited by LPCVD at 620℃ with SiH₄ gas 12. Mask#2：Define gate regions

13. Poly-Si wet etching by poly etching solution, gate oxide wet etching by BOE

14. Ion implantation：B, 10 K ev, 5 x 10¹⁵ ions/cm²

15. Dopant activation in N2 ambient at 950℃ for 30 min in furnace 16. 300nm oxide was deposited by PECVD as passivation layer 17. Mask#3：contact holes formed

18. 500nm Al thermal evaporation 19. Mask#4：Al pattern defined

20. Etching Al and removing photoresist

21. Al sintering at 450℃ in N₂ ambient for 30 minutes

The electrical properties of SiGe nanowire were measured with the contact pad served as source and drain, and substrate served as gate.

Chapter 3

Results and Discussions

We have successfully fabricated SiGe nanowire on silicon wafer, and the electrical characteristics of the nanowire were measured. In this chapter, SiGe test structure was fabricated and measured first and then SiGe nanowire structure followed. We make discussion on some key points in nanowire device fabrication and also on the measured electrical properties. We used HITACHI S-4000–FESEM to observe the nanowires and measure the size of them, and the I-V characteristics were measured by HP4156 semiconductor parameter analyzer.

3.1 Electrical property of SiGe films

3.1.1 Influence of Oxidation Time on Electrical Properties

Figure 3-1 shows I_D-V_G characteristics of four different devices:

un-oxidized, oxidation for 4 minutes, oxidation for 16 minutes, and oxidation for 36 minutes, respectively. Si_0.93Ge_0.07 film was used in this experiment. All of the oxidized devices were oxidized at 1000℃ minutes in dry ambient. The trend of the curves indicates that longer oxidation time would result in higher on current. Besides, after calculation, the On/Off ratios are 3.3, 1.6, 1.5 times higher than un-oxidized device for 36 min 16 min 4 min, respectively. In the longer oxidation time devices, more amount of Si was oxidized and achieves higher Ge concentration.

Same trend would be found in the I-V characteristics diagram.

Figure 3-2 represents I_D-V_D characteristics from different oxidation time devices. As predicted, 36 min-oxidized device has best on current, which is 5.08µA at VD = -8V. For the other devices, they are 1.52µA, 0.75µA, and 0.61µA for 16 min-oxidized, 4 min-oxidized, and un-oxidized device, respectively.

It is supposed that if Si in SiGe layer is fully oxidized, the performance of the SiGe-based p-MOSFET would always be improved since the positive correlation between the amount of oxidized Si and the mobility of SiGe channel.

3.1.2 Influence of Oxidation time for SiGe films

Figure 3-3 shows I_D-V_G characteristics of three different devices:

un-oxidized, oxidation at 950℃, and oxidation at 1000℃ at V_D = -5 V.

Si0.89Ge0.11 film was used. Both of the oxidized devices were oxidized for 16 minutes in dry ambient. It can be seen that oxidized devices shows better electrical performance than the un-oxidized one, and the device of 1000℃ shows even higher on current than the one of 950℃ while the both devices have roughly the same off current.

Figure 3-4 shows I_D-V_D characteristics which are consistent with the prediction：The device oxidized at 1000℃ has highest I_D of the three devices. For the other devices, they are 2.58µA, 1.83µA, and 0.40µA at V_D = -6V for 1000℃ oxidized, 950℃ oxidized and the un-oxidized, respectively.

According to above three diagrams, it is known that since SiGe got oxidized, Ge concentration got enhanced, and then mobility also increases which resulted in higher transconductance and on current. As the improvement of on current is higher than the increasing of off current, On/Off ratio then gets improved. With higher oxidation temperature, the oxidation rate would be higher, which makes more Si in SiGe layer got oxidized. Then the mobility would be even higher, and better performance is achieved.

3.2 Si

0.89

Ge

0.11

Nanowire shows the same behavior as test SiGe films

Figure 3-5 and Figure 3-6 show the ID-VD characteristics of Si_0.89Ge_0.11 nanowire. In Figure 3-5, the nanowire was not oxidized, and the gate length L = 6µm. In Figure 3-6, the nanowire was oxidized at 1000℃ 4min, the gate length L = 13µm. Clearly, higher current was obtained at negative gate voltages, demonstrating that the SiGe nanowire is a p-type semiconductor. The figure of ID-VD characteristics is somewhat nonlinear, which indicates non-ideal contact between the electrodes and nanowire. But as we know, there are still some reasons which affect the drive current including the diameter of the nanowire, wire length, the dopant condition, heat treatment, and the electrode contact, etc. So, if we want to compare the two structures, we should normalize them.

The equation about current I is

V I R I L ρ A

= ⋅ = ⋅ ⋅

, ρ is the resistivity.

We fix the voltage at V_D = 5V and V_G = -10V to be constant. Rewrite the

σ is the conductivity (Ampere per unit length) term and this is proportional to the current I and device length L. The area of the nanowire we could observe from the TFSEM. Figure 3-7(a) show the top view SEM picture and Figure 3-7(b) show the cross-section view SEM picture. There was fluctuation in each width and height which was controlled by the TCP dry etcher. The fluctuation must be decreased because the diameter of the nanowire is directly related to the current. So we make the average size of the Si0.89Ge0.11 nanowire. Additionally, we define the width of nanowire equal the width at half of height of the nanowire. We can obtain the average of the Si0.89Ge0.11 nanowire height is 85 nm and the width is 43 nm, we thought that the nanowire was a triangle column shape, so the average area is about 3655 nm². The Si_0.89Ge_0.11 nanowire at V_D=3V and V_G=-10V, by calculation, the Si0.89Ge0.11 nanowire current per unit length (conductivity) is σ = 10.65 A/cm for L = 6µm. For the oxidized the nanowire in figure 3-8, show the cross-section view. It is during 1000℃ oxidation and etching oxide by buffer oxide solution (BOE). It is found that the size of SiGe nanowire after oxidation is smaller than which is un-oxidized, due to what was already described above: Si atoms in the SiGe film was oxidized to form SiO₂, and was then removed by BOE solution. The height and the width

SEM, but the cross-section area of the oxidized nanowire is undoubtedly smaller than un-oxidized nanowire 3655 nm². Besides, as described in the previous section, Ge content in SiGe film would get increased after oxidation, it can be known that the Ge content in SiGe nanowire would also be higher than un-oxidized nanowire. From the above statements, it can be concluded that the conductivity of oxidized nanowire would be higher than un-oxidized nanowire.

3.3 Si

0.89

Ge

0.11

nanowire compare with Poly-Si nanowire

The SEM picture of Poly-Si nanowire fabricated by spacer process is shown in figure 3-9, and the I-V characteristics were compared with Si_0.89Ge_0.11 nanowire. Figure 3-10 shows I_D-V_D characteristics at different gate bias for Poly-Si nanowire with L = 8µm. As described in the previous section, the size of nanowire makes influence on electrical properties, so normalization of wire cross-sectional area, wire length, and bias voltage were made to achieve more accurate results. Data of SiGe nanowire before oxidation, SiGe nanowire after oxidation, and Poly-Si nanowire were listed in table 3-1. From this table, it is found that the conductivity of un-oxidized SiGe nanowire is higher than that of poly-Si nanowire, while the oxidized SiGe nanowire shows even higher conductivity.

Chapter 4 Conclusions

In our thesis, SiGe nanowire was successfully fabricated on silicon wafer with conventional lithography process. The electrical properties were measured by HP4156A and the structures of the SiGe nanowire on the sidewall spacer were observed by SEM. By our experiment of SiGe-based p-MOSFETs test structure, it is found that the devices of higher oxidation temperature and longer oxidation have more improvement in electrical properties. From the ID-VD characteristics, the same oxidation conditions were also performed for the SiGe nanowire and the same trench were achieved

Chapter 5 Future work

According to the literature nowadays, less research was done of the mechanism of SiGe. Oxidation temperature, oxidation time, interface reaction, and the content variation of Ge must be considered during the oxidation process. The influence of the thickness of SiGe film on the electrical characteristics is another way of researching. Whether the diffusion of Ge atoms makes higher concentration of GeO2 is also worth studying in the future.

Reference:

1. Physics of semiconductor Devices (Wiley-Interscience, New York, 1981), S. M. Sze, p.29.

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Electrochem. Soc. 149, G209 (2002)

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Electrochem. Soc. 149, G209 (2002)

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Kilpatrick, R. J. Jaccodine, P. E. Thompson, J. Appl. Phys. 93, 4896 (2003)

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Turban, J. Vac. Sci. Technol. B 20, 2281 (2002)

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Kilpatrick and R. J. Jaccodine, J. Appl. Phys. 81 8018 (1997).

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487-490 (2002)

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Nano Lett. 3(3); 343-346 (2003)

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1455-1457 (2001)

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Chou, Peter R. Krauss, and Preston J. Renstrom Science 272: 85-87 (1996)

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Length Current (A) Area Conductivity

Poly nanowire 8μm 5.68 x 10-⁷ 13839 nm² 1.095 A/V·cm

SiGe nanowire 6μm 3.99 x 10^-7 3655 nm² 10.65 A/V·cm S/D/Channel implant 10μm 9.72 x 10^-6 3655 nm² 88.65

A/V·cm After oxidation 13μm 8.99 x 10^-7 < 3655 nm² ---

Table 3-1 Conductivity σ = I · L /( V · A) ; Unit : A/(V·cm) at VD = 3V and VG = -10

Figure 1-1. Oxygen peaks of backscattering spectra for pure Si and samples containing, respectively, 25, 50, and 75 at.% Ge, after 45 min oxidation at 900 “C.

Figure 1-2. The total amounts of Ge atoms after oxidation normalized by those before the oxidation as a function of oxidation time for the SGOI layers with initial thicknesses of 70 ± 10 nm (^○) and 320 nm (●)

Figure 1-3. Rate of oxidation of Si and SiGe; (a) wet oxidation, 800℃; (b) dry oxidation, 800 and 1000℃.

Current Current Preamplifier

Preamplifier LockLock--in Amplifierin Amplifier Current Metal--Coating TipCoating Tip

T.T.

Preamplifier LockLock--in Amplifierin Amplifier Current Metal--Coating TipCoating Tip

T.T.

Preamplifier LockLock--in Amplifierin Amplifier Current Metal--Coating TipCoating Tip

T.T.

Preamplifier LockLock--in Amplifierin Amplifier Current Metal--Coating TipCoating Tip

T.

Figure 1-4. Schema of Scanning Probe Lithography (SPL).

Figure 1-5. Schematic process flow of nanoimprint (a) After nanoimprint and removal of residual PMMA by O2 plasma (b) Pt evaporation and lift-off.

(a)

(b)

Figure 1-6. (a) Binary Phase Diagram for the Au:Ge. (b) An SEM image of Ge nanowires synthesized by CVD at 275℃ on a SiO₂/Si substrate.

The inset shows an AFM image of Au nanoclusters on the substrate recorded prior to CVD.

Figure 1-7 Schematic view of iterative spacer lithography (ISL).

.

Figure 2-1. Define AA region.

Figure 2-2. Deposition α-Si + SiGe.

Mask 1 SiO2

αSi + SiGe SiO2

Figure 2-3. Define S/D region.

Figure 2-4. Etching over two side spacer.

Mask 2 αSi + SiGe SiO2

Mask 3 αSi + SiGe SiO2

Figure 2-5. Define Bottom gate via.

Figure 2-6. Al contact.

Mask 5

Gate Gcontact hole αSi + SiGe

SiO2

Mask 6 Al

S/D/G Gcontact hole αSi + SiGe

SiO2

Figure 2-7. The completed test SiGe MOS structure.

Silicon substrate

Thermal oxide

SiGe

P

⁺

P

⁺

TEOS oxide

Poly Gate

TEOS Passivation

Al pad

Figure 3-1. ID-VG transfer characteristics of different oxidation times of the test structure；W/L = 1 µm/µm at VD = -5 V.

Figure 3-2. I_D-V_D transfer characteristics of different oxidation times of the test structure；W/L = 1 µm/µm at V_G - V_t = 3V.

Figure 3-3. I_D-V_G transfer characteristics of different oxidation temperatures of the test structure；W/L = 1 µm/µm at V_D = -5 V.

Figure 3-4. ID-VD transfer characteristics of different oxidation temperatures of the test structure；W/L = 1 µm/µm at VG - Vt = 3V.

Figure 3-5. SiGe nanowire I_D - V_D characteristics before oxidation.

Figure 3-7. (a), (b) The cross-section view of Si0.89Ge0.11 nanowire observed by SEM.

(a)

(b)

Figure 3-8. The cross-section view of Si_0.89Ge_0.11 nanowire after oxidation observed by SEM.

Figure 3-9. The cross-section view SEM picture of Poly-Si nanowire

-4 -2 0 2 4 -1.5

-1.0 -0.5 0.0 0.5 1.0 1.5

ID (µA)

VD (V) -10V

-5 V 0 V +5 V +10V

Figure 3-10 Poly-Si nanowire ID - VD characteristic ( L = 8μm , VG = -10 ~ 10 V )

簡歷

姓 名：吳恆信 性 別：男

出生日期：民國 70 年 10 月 16 日 出 生 地：高雄市

住 址：高雄市三民區黃興路 417 巷 21 號

學 歷：國立聯合大學電子工程系 (民國 88 年 9 月~民國 90 年 6 月) 國立高雄應用科技大學電子工程系 (民國 90 年 9 月~民國 93 年 6 月)

國立交通大學電子工程所 (民國 93 年 9 月~民國 95 年 9 月)

碩士論文：矽鍺奈米線在不同製程條件下之電特性研究

A Study of Electrical Properties under Various Process Conditions for SiGe Nanowire

在文檔中 矽鍺奈米線在不同製程條件下之電特性研究 (頁 22-0)