In the following section, the chapter 2 presents the architecture of 8T SRAM cell and DADS circuitry, and illustrate the operations of these circuitry. This chapter also states experimental setup we used for simulation. Chapter 3 introduces three methods we used for testing, including: March C-, floating bitline attacking (FBA), and self-loop attacking (SLA). Chapter 4 shows the experiment results of these testing methods, and explain the meaning of results. Chapter 5 is the overall conclusion.
Chapter 2
Preliminary of the low-Vmin data-aware dynamic-supply 8T SRAM
2.1 Introduction of architecture and operations
Before the discussion of defect and testing, we firstly introduce the low-VMIN data-aware dynamic-supply 8T SRAM and its operations. Figure 1 shows the
schematic of the SRAM. The cell is as the lower part in the figure composed by M1–M8, and the data-aware dynamic supply circuitry is as the upper part with M9–M12.
Figure 1
Schematic of the low-VMIN data-aware dynamic-supply 8T SRAM.
The SRAM cell holds data by the cross-coupled inverter M1–M4. Read
operation relies on the independent path M7 and M8. To write-0, BL is set to zero and connects the Q through ”M5 and M7”. If write-1, BL is still set to zero but QB on the
contrary will be connected to through ”M6 and M7”. Table 1 summarizes the controls for the 8T SRAM including the row-based WL and column-based WWLA/WWLB, BL, and VVSS. The read-write word-line (WL) turns on for both read and write, but WWLA/WWLB turn on only for write. Besides, depending on the written data, only one of WWLA/WWLB is on during the write. BL is floating-1 when read and 0 for write. The VVSS, mainly used for read operation, is suggested to follow WWLA to prevent the write disturb of background cells [21].
Table 1
CONTROL SIGNALS FOR THE 8T SRAM CELL
Read 0 Read 1 Write 0 Write 1 Hold
WL 1 1 1 1 0
BL Precharge Precharge 0 0 X
WWLA 0 0 0 1 0
WWLB 0 0 1 0 0
VVSS 0 0 0 1 0
The data-aware dynamic-supply (DADS) circuitry, shown as M9–M12 in Figure 1, controls the supply voltage (VDDA and VDDB) for the cells in column.
With WWLA and WWLB as the inputs, either M9 or M10 would be turned off when one of the cells in column is being written. For example, when a cell in the column is at write-1, WWLA is high for BL accessing and pulling down the QB. The M10 is then turned off, and pMOS M2 will get lower supply current from VDDA since only M12 provides that. The DADS then assists the write-1 operation because QB can be pulled down easily. For write- 0, WWLB is high and M9 is turned-off on the contrary.
The DADS circuitry assists the write-0 by leaving only M11 supporting VDDB. The supply-level (SL) controlling M11 and M12 is set to provide a minimum supply
current for the background cells at write periods. Thus, there is a voltage upper bound for SL. SL still has a voltage lower bound. It’s because the SL with voltage too low
will turn on M11/M12 too much, which makes VDDA/VDDB always with high supply capability. The data-aware write-assist function would then be canceled.
2.2 Experimental setup
In our experiments, we apply a 256Kb DADS 8T SRAM with eight 32Kb blocks. Each block is composed by 256 rows and 128 columns. Thus a DADS circuitry drives 256 cells in column. The SL is set to 0.5*VDD (VDD=0.6V) which
has been verified that the 8T SRAM can operate correctly from process corner SS to
FF. For most of our experiments, we run the simulation under TT corner. Only for our proposed test method, we consider all the process corners to prove the method’s
validity. This will be shown in the sections later.
Chapter 3 Test methods
3.1 Test Methods & Minimum detectable resistance
To detect open defects, Three methods including March C- algorithm, floating bit-line attacking (FBA), and self-loop attacking (SLA) are used. The defects are
simulated by injecting a resister into each MOSFET of the SRAM and DADS
circuitry with resistance swept from high (100GΩ) to low. For each single defect, we
record the minimum resistance when the SRAM's sense amplifier reports error. If the defect does not fail the SRAM even with 100GΩ, it is considered undetectable.
Explanation of FBA and SLA are for the following parts.
3.2 Floating bit-line attacking (FBA)
According to the non-conventional SRAM categorization in [20], the 8T SRAM should be categorized to "Type-A". However, the corresponding test method
recommended for the defects at cross-coupled inverters requires dual bit-lines during the test. For the 8T SRAM which has only one bit-line, the method is not applicable.
We select the floating bit-line attacking (FBA) method which is for another type of SRAM in [20] but can be modified for single-bit-line based SRAMs. FBA uses the
floating voltage pre-set on bit-line to access and attack the Q (or QB) with inverse logic in the cell. If the data stored in the cell flips, the following read operation can then detect the defect.
Figure 2
An example of floating bit-line attacking method:
using floating-0 on bit-line for detecting the open defects R1.
Figure 2 shows an example of using floating-0 as the attacking source on BL.
The open defect R1 at M1 is the target to test. As shown in the figure, the Q/QB need to be 1/0 initially. The BL with floating-0 is accessing/attacking the Q through the turned-on M5 and M7. If the open defect makesM1 unable to maintain the 1 on Q, the sense amplifier will output 0 in the following read operation. The defect is then
detected. Note that BL with floating-1 can also be applied for detecting R1 if QB is accessed/attacked through M7 and M6 instead. Table 2 lists the complete control signals of FBA for the four open defect locations. WL turns on for every cases. The initial Q/QB value is set depending on the defect locations: 1/0 for M1/M4 and 0/1 for M2/M3. As to WWLA/WWLB, they control the attacking source accessing the node with inverse logic. Besides these control signals, there are still two factors would affect defect detection: the value of VVSS and background cells. Further discussion would be the next section.
Table 2
CONTROL SIGNALS OF THE FBA TEST METHOD Defect Location Attacking SRAM. The SLA method utilizes the specific dual-write-pass-gate structure of the 8T SRAM cell. By controlling the word-lines, the method creates an internal attacking loop of Q/QB inside the cell without BL’s accessing. The Q and QB with
self-attacking each other will go to a final state which depends on the initial Q/QB, background cells, VVSS, process corners, and the most important one: the existence of defects. If the defects result in a different final state from that of defect-free cells, the following read operation can then detect the faults.
Figure 3
Configuration of the proposed self-loop attacking test method.
Figure 3 shows the configuration of the method. Before the test, Q and QB can store either 1/0 or 0/1. During the test, M7 is off and M5/M6 are on so that Q and QB inside the cell will attack each other. After the test, WWLA/WWLB is off, and the final state of the cell is read. Note that, since the BL is not used during the SLA, the test operation hence has chances to be done for the whole array at one time. Although
defects not only in the cross-coupled inverters of the cell but also in the DADS circuitry.
Chapter 4 Experiment results
4.1 March C-
Table 3 lists the simulation results of the test. The first two columns are the device type and the device name at which the defect is injected. The third and fourth columns are the detecting operation and the minimum detectable resistance. The word
"undetectable" means the fault injection does not fail the SRAM even with 100GΩ.
Table 3
TEST RESULTS OF MARCH C- FOR OPEN DEFECTS Device type Device
As shown in the table, the defects at pull-down nMOSs and in the DADS circuitry are undetectable. For the pull-down nMOSs (M3 and M4), the defects fail neither the write nor the read. In write, Q or QB can always be successfully pulled down by the BL even if the pull-down nMOSs are defective. In read, the independent read path would take charge to transmit the data to the floating-1 on BL in place of the original pull-down nMOSs in 6T SRAM. Thus, normal operations cannot detect the
defects. As to the DADS circuitry, when the defect occurs at M9 and M10, the fault is masked. It’s because M9 and M10 are originally set to off when write. And even when
read/hold, the defect-free M11 and M12 will help support VDDA and VDDB that the stored data never flip due to the defect at M9 and M10. While defects occur at M11 and M12, the background cells do get weak supply from VDDA (or VDDB) when certain cell in the column is written. But the simulation results show the background cells can hold the data correctly during the write period and until M9 or M10 is re-turned on at the end of the write. Thus, the defects at M11 and M12 are also undetectable.
In addition to the pull-down nMOSs and the DADS circuitry, the defects at pull-up pMOSs (M1 and M2) are also belonged to hard-to-detect ones. Although the defects are detected by write operations according to Table 3, the min-detectable resistance is at 500M–800M. This implies the defect could be detected only if the
resistance is large. Hence, we still need other test methods for lowering the detectable resistance.
Open defects at the pass-gates (M5, M6, and M7) and read-path transistor (M8) can be easily detected by write and read operations respectively. The minimum detectable resistance is at MΩ or below. Note that the minimum detectable resistance of the defects at M5 and M6 will vary depending on the data stored in the background cells. As shown in Table 3, when all the background cells store 0, the write operation in the March can detect lower open resistance for both the cases. However, the
reasons for the two are different. For the defect at M5, when the defective cell is being tested by the write-0 operation, the Q is being pulled down by the BL, and QB is being pulled up by pMOS M2 with VDDA supply (see Figure 1). While all the
background cells store 0, most cells share the VDDA since the corresponding QBs are 1. Hence, the background setting with all 0 causes the most severe write operation for the defective cell. Lower resistance is then detected.
As to the defect at M6, the background cells affect the testing via VVSS unlike the VDDA in the previous case. Figure 4 shows corresponding details with turned off pass-gates ignored.
Figure 4
Background effect to VVSS when open defect at M6 is being detected.
In the figure, the above cell is the defective one being tested by a write-1
operation. The initial data in the cell is Q/QB=0/1. The cell below represents the 255 background cells also with Q’/QB’=0/1. In the figure, all the turned-off pass-gates are
ignored. Firstly, the BL is accessing and attempting to pull down the QB through M7 and M6. Before the write operation completes, the M8 remains turned on since the QB is originally 1. The turned-on M8 connects VVSS and VP . The voltage on VP is then not a perfect zero since it’s not only driven by the BL through M7 but also driven
by the VVSS driver through M8. While the background cells all store 0 as shown in the figure, VVSS further connects to VDDA through the M'8, M'6, and M'2 in the background cells. The connection of VVSS–VDDA then raises the voltage on VP
much more. As a result, to succeed the write-1 becomes harder and lower resistance is detected.
To summarize, the March C- detects the defects at M5–M8. For M5–M6, the minimum detectable resistance can be further lowered if all the background cells are set to 0 for write-0 and write-1 respectively. The algorithm {⇕(w0); ⇕ (w1,r1,w0,r0)}
as example can achieve the goal. As to the defects at the cross-couple inverters M1–M4 and the DADS circuitry M9–M12, they are either undetectable or
hard-to-detect. In the following section, we will introduce the test methods for the detects.
4.2 Floating bitline attacking (FBA)
Table 4 shows the test results of FBA. The first column is the attacking source on bit-line. The second and the third columns are the background cells' data and the VVSS logic during the test. The rest of the table lists the test results of the four open defect locations respective.
Table 4
TEST RESULTS OF THE FBA TEST METHOD Attacking undetectable. For the detected results, the table lists the minimum detectable
resistance. For overtests marked "X", the stored data will flip even the SRAM cell is defect-free. Hence, it is also inapplicable as the undetectable cases marked "-".
According to the results, the defect at M1 in never detected since floating-0 in FBA will cause overtest, and floating-1 does not detect any data flipping. However, to M2, floating-0 in FBA with VVSS=1 is applicable for detecting the defect. The minimum detectable resistance is 1MΩ∼3MΩ. For nMOSs M3 and M4, floating-1 is
more appropriate than floating-0. The minimum detectable resistance of the defect is 5MΩ∼30MΩ and 10MΩ∼30MΩ for M3 and M4 respectively.
The difference of M1 and M2 is the impact of VVSS. For floating-0, Q/QB is 1/0 for M1. M8 does not turn on while QB is 0; therefore, VVSS does not connect to
the cell. However, Q/QB is 0/1 for M2. In this situation, VVSS connect the cell directly. When VVSS is 0, it strengthen floating-0 attacking and results overtest. On the contrary, if VVSS is 1, it weaken floating-0 attacking and results detectable. For detectable two cases, the minimum resistance of BG sets to 0 is lower than BG sets to 1. It is because if BG sets to 0, VDDA need to supply voltage to cell and background.
It means VDDA has larger loading and makes it harder to hold cell's QB. Threfore, the defect can be detected by lower resistance.
For M3, only BG/VVSS sets to 1/0 in floating-0 would result overtest. It is because if BG is 1, VDDA only supply voltage for cell's QB and makes it stronger to turn on M8. When VVSS is 0, it would strengthen floating-0 attacking which results overtest. In floating-1 test, BG/VVSS sets to 0/1 or 1/1 can detect defect. The reason is that initial Q/QB for testing M3 is 0/1 and VVSS strengthen floating-0 attacking.
Setting BG/VVSS to 1/1 can detect the lowest detectable resistance because setting BG to 1 makes cell's QB stronger (no BG cells share VDDA), and results floating-1 attacking stronger.
For M4, floating-0 attacking cannot detect defect and the result depends on BG.
when BG sets to 0, cell's Q is stronger. Floating-0 attacking does not make the cell fail to hold data. However, if BG sets to 1, cell's Q is too weak that even defect free cell cannot hold data. Because the initial Q/QB set of testing M4 is 1/0, the influence of
VVSS is weaker. Except for BG/VVSS sets to 0/0, other cases in floating-0 can detect defect. While BG sets to 0, Q is stronger and M4 is more sensitive. When QB close to 1 and turns on M8, the value of VVSS would impact the result. If VVSS sets 0, it weaken floating-1 attacking and results in undetectable. If VVSS sets 1, the defect is detectable. While BG sets to 1, Q is weaker and M4 is less sensitive. In this situation, floating-1 can detect defect no matter what value VVSS is.
For test time, FBA requires two operations for each defect on each cell. One is the floating bit-line attacking, and the other is a simple read. Here we ignore the preliminary write operation before each FBA since the 1N operation can usually be omitted by reordering the test elements in March. The total number of operations for the complete FBA is hence 2Nx3 for defects at M2–M4. Note that, although
floating-1 in FBA which detects the defects at M3 and M4 are with the same BG and VVSS as shown in Table 4, the actual setups for the two are different. As shown in Table 2, the initial Q/QB set for M3 and M4 should be different. Therefore, detections for M3 and M4 require individual test time 2N for each.
4.3 Self-loop attacking (SLA)
4.3.1 Test for 8T SRAM cell
Table 5 shows the simulations results of the test under process corner TT. The first two columns are the eight possible configurations. The iTG means the ”initial”
state of the target cell under the SLA test. iBG is the initial data stored in the
background cells. The third column shows the final states of defect-free SRAMs with the corresponding configuration at left. For example, in Config. 1, the target cell and background cells before the test are both set initially to 0. VVSS is also 0. After test, the final states of target cell and background cells both become 1. The background cells have their data changed because their WWLA/WWLB are shared with the target cell. The turned-on WWLA/WWLB also cause the Qs and QBs in background cells attacking each other. Based on the final states in the third column, the open defects causing different ones will be detected by the read operation afterwards. The rest of the table lists the minimum detectable resistance of the defected open defects.
Table 5
FINAL STATES OF DEFECT-FREE CELLS AND TEST RESULTS OF OPEN DEFECTS OF SLA UNDER PROCESS CORNER TT
Config. (i)BG: (initial) data of the 255 background cells
For M1, there are 5 Config. can detect defect and the minimum detectable resistance is 10MΩ. All of final states of these Config. are 1. The value of Q of Config.
7, and 8 are 1→1. It is easy for Q to hold data, and the detect resistance is 800MΩ
which is larger than other Config. setting. For Config.1, 2, and 4, M1 has to pull up Q.
Therefore, the detect resistance is smaller. The difference of Config. 1 and 2 is the value of VVSS. Due to the initial setup of Q/QB is 0/1, QB turn on M8 and makes VVSS impact the cell. While VVSS is 0, it is harder for M1 to pull up Q and makes M1 more sensitive.
For M2, only Config. 5 and 6 can detect defect. The value of Q of Config. 5 and 6 are 0→1. QB has to pull down QB. Similar to test M1, the difference of Config. 5
and 6 is the value of VVSS. When VVSS sets to 1, it can detect the minimum
detectable resistance 10KΩ. It is because the cell is construct of nMOS and VVSS has
greater influence while it is 0. After SLA, WWLA and WWLB are turned off. If VVSS is 0, the voltage of Q is lower; oppositely, if VVSS is 1, the voltage of Q is higher. The original final state of Q is 0. Thus, VVSS sets to 0 is easier to make Q pull down than sets to 1.
The minimum detectable resistance of M3 is 8KΩ. It is similar to M2 because
M3 and M2 are symmetrical. Same as M2, only Config. 5 and 6 can detect defect of M3. The value of Q are 0→1 and M3 has to pull down QB. If VVSS sets to 1, the
voltage of Q is higher and makes M3 more sensitive.
For M4, Config. 1 and 4 can detect defect, and the value of Q are 0→1. It is interesting that Config. 2 is also 0→1, but this setting cannot detect M4. The
difference between Config. 1 and 2 is the value of VVSS. The initial setup of Q/QB of
difference between Config. 1 and 2 is the value of VVSS. The initial setup of Q/QB of