After introduction of Chapter 1, the device fabrication will be discussed in Chapter 2. Then characteristic of space-charged-limited transistors will be described in chapter 3. The self-assembled-monolayer will be analyzed in Chapter 4. Finally, conclusions will be given in Chapter 5. The section organization of this thesis is listed below:
Et: electrons or holes trap states EFN: electrons or holes Femi-Level Et: electrons or holes trap states EFN: electrons or holes Femi-Level
Chapter 1
Figure 1.1 The injection charge which can not transport or recombine immediately, and accumulate in the metal-semi interface.
Figure 1.2 Band diagrams of deep traps and shallow traps.
Chapter 2
Device Fabrication
2.1 Device Structure and Fabrication
2.1.1 Device structure and cross-section
Figure 2.1 shows the structure of space-charge-limited transistors. Bottom silicon oxide is used to block the leakage current between Al and Au, and the top silicon oxide is used to block the leakage current between Al and Al. There are three organic materials will be discussed such as poly [3-hexylthiophene] (P3HT), pentacene and fullerene (C60). The cross-section of device and the device dimension is 1mm2. Figure 2.2 shows the process flow of the vertical transistor proposed in this work.
2.1.2 Glass substrate clean
Glass substrate (CORNING Eagle 2000) must keep clean or films may become rough. The rough surface would cause point discharge between the insulator and metal. The steps of clean glass substrate are shown as.
Steps:
(1) De Ion (DI) water current flows for 5 minutes in order to remove the particles.
(2) The substrates should be placed under the in the acetone and ultrasonic resonance for 5 minutes in order to remove the organic pollution. Then, the substrates have to put under the DI water current flow for 5 minutes in order to remove the solvent.
(4) The substrates were put in the KG detergent bath with ultrasonic resonance for 5 minutes in order to remove the particles, fingerprint, and ionic.
(5) The substrates were put under the DI water current flow for 5 minutes in order to remove the solvent.
(6) Finally, the substrates would be fried with dry N2 flow to blow off the water on the substrates.
2.1.3 Bottom metals deposition
Before deposition metal on the substrate, the glass substrates were exposed to the UV-light by UVO3 clean machine that keep the substrate surface clean. Nickel(99.99
) was deposited to increase the adhesion of the Gold by thermal evaporator. The deposition rate was controlled at 1Å/sec and the thickness of nickel was about 100Å.
After deposition of adhesion layer, Gold (99.99%) was deposited by thermal evaporator. Both of two processes the deposition pressure was started at 5x10-6torr and the substrates temperature fixed at 50°C. The metal region was defined through shadow mask.
2.1.4 High Density Polystyrene Spheres as Shadow Mask
It could fabricate a microstructure in the lateral direction within a large scale organic device using non-photolithographic processes according to Spontaneous Patterning of Higher Order Structures’ (SPHOS) [41–43]. Colloidal lithography [44], one of the techniques adopted in the SPHOS forms porous films by removing particles after the film deposition. Positively charged polystyrene particles shown in Figure 2.3(a) (200 nm, tetramethylammonium latex) were adsorbed onto the substrates from dispersion by electrostatic interactions. Particles concentration diluted with ethanol to 0.6 wt%. Immersion time was 3 minutes to allow the adsorption to reach saturation. Excess particles were rinsed off in a beaker with ethanol and then transferred to a beaker with boiling isopropanol solution for ten seconds. Figure 2.3(b) shows polystyrene spheres are absorbed on the Au film surface. After the SiO/Al/SiO
deposition, the polystyrene spheres are removed by an adhesive tape (Scotch, 3M) without damage to the metal. The images of the Al grid with 2000 Å opening diameter are shown in Figure 2.3(c). The key procedure in this fabrication is that the substrate is then transferred to a beaker with boiling isopropanol solution for ten seconds. Similar to the method of Fujimoto et al [24], the substrate is finally blown dry immediately in a unidirectional nitrogen flow. The boiling isopropanol treatment is a critical step to achieve a high density yet separated array of holes, required for vacuum tube triode as well as SCLT. When the substrate is submerged in polystyrene solution, the charged polystyrene spheres are absorbed on the Au surface without aggregation due to the electrostatic repulsion force. The polystyrene spheres without the boiling isopropanol treatment shown in Figure 2.3(d) are easy to aggregate during the drying process and cause unwanted non-uniform and connected distribution. This may be attributed to the capillary force which pulls spheres into aggregates before the spheres are immobile during the period of vaporized solvent. The importance of the boiling isopropanol treatment is presumed to increase the evaporation rate of the solvent during the nitrogen blow dry such that the spheres do not have enough time to move to one another and form aggregate during evaporation. By tuning the solution concentration and submerging time, the condition to prepare Al grid with maximum opening density with minimum unwanted openings can be found in spite of some occurrence of the unwanted irregular openings The benefit of this method is the possibility to process large areas in a short processing time without photolithography.
2.1.5 Dielectric and grid fabrication
After immersed polystyrene spheres as shadow mask, the deposition is started at the pressure around 3×10-6torr. Slower deposition rate is expected to result in smoother and better ordering of the insulator than fast one. The 50-nm-thick silicon oxide was deposited by thermal evaporation at a deposition rate of 0.1Ǻ/s. It is
evaporated to prevent large leakage current from Al to Au. The insulator region was defined through shadow mask. Then we deposited aluminum as base metal. The deposition is started at the pressure around 5×10-6torr. The 30-nm-thick Al was deposited by thermal evaporation at a deposition rate of 1Ǻ/s.
2.1.6 Organic active layer fabrication
In the section, introduce each of the organic layer deposition respectively:
1. P3HT:
The substrate was exposed under the ultra-violate light for 15min to keep surface clean. P3HT was spin coated from chlorobenzene solution (2.5 wt% 1000rpm) on the Au layer, and baked at 200 °C for 10min in vacuum. After we spin coated the P3HT film, we use acetone to clean the unnecessary area. Then, a thin P3HT layer of about 1338 Å was obtained.
2. Pentacene
The substrate was exposed under the ultra-violate light for 15min to keep surface clean. The pentacene material obtained from Aldrich without any purification was directly placed in the thermal coater for the deposition. The deposition was started at the pressure around 3×10-6torr. The 180-nm-thick pentacene was deposited by thermal evaporation at a deposition rate of 1Ǻ/s. The active region was defined by shadow mask.
3. C60
The substrate was exposed under the ultra-violate light for 15min to keep surface clean. The C60 was directly placed in the thermal coater for the deposition. The deposition was started at the pressure around 3×10-6torr. The 200-nm-thick C60 was deposited by thermal evaporation at a deposition rate of 1Ǻ/s. The active region was defined by shadow mask.
2.1.7 Top metal deposition
and PackageWe deposited Al as the top metal. The deposition was started at the pressure around 5×10-6torr. The 50-nm-thick Al was deposited by thermal evaporation at a deposition rate of 1Ǻ/s.
If life time of device becomes longer, the sample should be packaged to avoid the oxygen and moisture. The device were packaged in the glove box filled with the N2 gas and sealed the cap for sample protection. We sealed the cap by the glue which crosses link as it exposed under the ultra-violate light for proper time where the wave length is 356nm. The process flow of the vertical transistor was proposed in this work.
2.2 Dielectric characteristics
From Figure 2.4(a), we can get the different breakdown voltage corresponding to different thickness of silicon oxide. When the operating voltage is 1V with thickness of bottom dielectric is 50 nm, the leakage current level is 10-3mA/cm2. When the operating voltage is 1V the leakage with thickness of top dielectric is 30 nm, the leakage current level is 10-2 to 10-3mA/cm2. The current of transistor can be low off depending on these measurement results.
Figure 2.4(b) shows comparison the characteristics of silicon oxide with/without Polystyrene Spheres. From Figure 2.4(b), the leakage current of silicon oxide significantly increase after used Polystyrene spheres as mask. The reason is Polystyrene Spheres occupied the location of silicon oxide (SIO). It is inevitable in the process of Polystyrene Spheres.
Au(400A) S i O (5 00A)Al (400A) S i O (3 00A) Organic Al (5 00A)
Organic
2 000A
Hole size:2000A
Au(400A) S i O (5 00A)Al (400A) S i O (3 00A) Organic Al (5 00A)
Organic
2 000A
Hole size:2000A
Chapter 2
Figure 2.1 The structure of space-charge-limited transistor.
Figure 2.2 The process flow of the vertical transistor proposed in this work.
(a) (b)
(c) (d)
(a) (b)
(c) (d)
Figure 2.3(a) The structure of polystyrene spheres.(b) The polystyrene spheres on the Au film surface.(c) The polystyrene spheres are removed by an adhesive tape (Scotch, 3M) without damage to the metal. (d) The gold surface without the boiling IPA treatment.
-1.0 -0.5 0.0 0.5 1.0 10-6
10-5 10-4 10-3 10-2 10-1 100 101
E(MV/cm)
J(mA/cm
2 )
with Polystyrene Spheres without Polystyrene Spheres
-1.0 -0.5 0.0 0.5 1.0
10-4 10-3 10-2 10-1
J(mA/cm
2 )
E(MV/cm)
(a)
(b)
Figure 2.4(a) The characteristics of silicon oxide with Polystyrene Spheres. (b) Comparison the characteristics of silicon oxide with/without Polystyrene Spheres.
Chapter 3
Result and Discussion
3.1 Transfer characteristic of SCLT
3.1.1 P3HT-based space-charge-limited transistor
P3HT-based SCLT was fabricated based on chapter 2. The characteristics of P3HT-based SCLT with opening diameters of 2000 Å on the top insulator (SIO) are shown in Figure 3.1 (a). In P3HT-based SCLT the carriers in the Al grid are blocked by the 30-nm silicon oxide and 14-nm P3HT between Al (base) and Al (collector).
The grid current is the reverse current of the Al/SIO/P3HT/Al diode which is almost zero. The current gain is an important value to be maximized. As shown in Figure 3.1 (a) and Figure 3.1 (b), the grid current density (JG) of P3HT-based devices is in the order of 10-5 mA/cm2 which is much smaller than JC. The current gain which is defined JC/JGis as large as 104. The collector current (JC) for fixed collector voltage is modulated by the grid voltage (VG) and the Au (emitter) is the common ground.The positive grid voltage VG, is used to introduce energy barrier for holes at the openings, and the off current can be reduced by increasing VG until a large leakage current between the grid and collector occurs. Figure 3.1(a) shows the on/off ratio of JC is 24310 at VC = – 1 V for transistors with opening diameters of 2000 Å on the top insulator and the highestJC output is 1.331mA/cm2in for device dimension is 1 mm2. The total output current can be scaled up by using a larger area in the same condition.
The device characteristics in double logarithmic scale with fixed VG are shown in Figure 3.2 for tracing the signature of SCLC. Three regions belonging to ohmic, trap filling and SCLC can be distinguished [45]. The slope of log I − logV is equal to 1 for ohmic conduction, while the slope is equal to 2 for SCLC. The dashed lines with slope equal to 1 and 2 are drawn in the Figure.3.2 for indication. Indeed, the current
follows the SCLC once the barrier at the opening is suppressed by a sufficiently negative VC. There is always a small ohmic current at the low voltage. The polymer diode has a turn-on voltage where the current varies from a small leakage ohmic current to a quadratic SCLC current. The turn-on voltage is determined by both the level of the leakage and the difference between the work functions of the cathode and anode. Figure3.2 is shown the P3HT-based emitter-collector diode and the SCLC is about 3V.
3.1.2 Pentacene-based space-charge-limited transistor
Pentacene-based SCLT was fabricated based on chapter 2. The characteristics of Pentacene-based SCLT with opening diameters of 2000 Å on the top insulator are shown in Figure 3.3(a). In Pentacene-based SCLT the carriers in the Al grid are blocked by the 30-nm silicon oxide and 60-nm Pentacene between Al (base) and Al (collector). The grid current is the reverse current of the Al/SIO/Pentacene/Al diode which is small but not zero. The current gain is therefore an important value to be maximized. As shown in Figure 3.3(a) and Figure 3.3(b), the grid current density JG
of Pentacene-based devices is in the order of 10-3mA/cm2 which is much smaller than JC. The current gain which is defined JC/JGis as large as 103. The collector current (JC) for fixed collector voltage is modulated by the grid voltage (VG) and the Au (emitter) is the common ground.The positive VG is used to introduce energy barrier for holes at the openings, and the off current can be reduced by increasing VGuntil a large leakage current between the grid and collector occurs. Figure 3.3(a) shows the on/off ratio of JC is 390 at VC = – 1 V for transistors with opening diameters of 2000 Å on the top insulator and the highestJC output is 0.2693mA/cm2for device dimension of 1 mm2. The device characteristics in double logarithmic scale with fixed VG are shown in Figure 3.4 for tracing the signature of SCLC. The dashed lines with slope equal to 1 and 2 are drawn in Figure 3.4 for indication. Indeed, the current follows the SCLC
once the barrier at the opening is suppressed by a sufficient negative VC. There is always a small ohmic current at low voltage. The polymer diode has a turn-on voltage where the current varies from a small leakage ohmic current to a quadratic SCLC current. The turn-on voltage is determined by both the level of the leakage and the difference between the work functions of the cathode and anode. Figure3.4 is shown the P3HT-based emitter-collector diode and the SCLC is about 4V.
3.1.3 C60-based space-charge-limited transistor
C60-based SCLT was fabricated based on chapter 2. The characteristics of C60-based SCLT with opening diameters of 2000 Å on the top insulator are shown in the Figure 3.5(a). In C60-based SCLT the carriers in the Al grid are blocked by the 30-nm silicon oxide and 80-nm C60 between Al (base) and Al (emitter). The grid current of Al/SIO/C60/Al diode is almost zero. Therefore, the current gain is an important value to be maximized. As shown in Figure 3.5(a) and Figure 3.5(b), the grid current density (JG) of C60-based devices is in the order of 10-3 which is smaller than JC. The current gainJC/JGis as 102. The collector current (JC) for fixed collector voltage is modulated by the grid voltage (VG) and the Al (emitter) is the common ground. The negative VG is used to introduce energy barrier for electrons at the openings, and the off current can be reduced by decreasing VG. Figure 3.5(a) shows the on/off ratio of JCis 589 at VC= 1 V for transistors with opening diameters of 2000 Å on the top insulator and the highestJC output is 0.411mA/cm2for device dimension area of 1 mm2. The total output current can be scaled up by using a larger area. The device characteristics in double logarithmic scale with fixed VG are shown in the Figure 3.6 for tracing the signature of SCLC. The dashed lines with slope equal to 1 and 2 are drawn in the Figure 3.6 for indication. Indeed, the current follows the SCLC once the barrier at the opening is suppressed by a positive enough VC. At low voltage there is always a small ohmic current. The polymer diode has a turn-on voltage where
the current switches from a small leakage ohmic current into a quadratic SCLC current. The turn-on voltage is determined by both the level of the leakage and the difference between the work functions of the cathode and anode. Figure3.6 is shown the P3HT-based emitter-collector diode and the SCLC is about 2V.
3.2 Operation mechanism
The operation mechanism of the polymer SCLT can be understood as the quadratic space-charge-limited current between the emitter and the opening modulated by the grid potential. The potential at the center of the opening is a linear combination of grid and collector potential µVG +VC in vacuum tube. The factor µ depends on the device geometry and increases with the ratio between the opening diameter and the grid-collector distance. The SCLC between the emitter and the opening is therefore approximatelyCεµ
(
λVG +VC)
2/ L3, where ε is the polymer dielectric constant and L is the emitter-top insulator distance. If the potential across the opening were uniform, the factor C would be the standard SCLC value of 9/8. The overall effect of non-uniform potential in our case can be absorbed into a numerical factor C. Because of the higher electric field, the space between the grid and the collector does not limit the collector current. Therefore the emitter-opening current given above is actually the output current. In this section, P-type (P3HT and Pentacene) and N-type (C60) are introduced respectively.1. P3HT and Pentacene (P-type)
The grid control of the current can be further illustrated by looking at the spatial distribution of the current across the opening. For P3HT and Pentacene, some region near the center of the opening has negative potential for holes to pass through. The effect of the grid near the edge is so significant that a potential barrier forms despite of the negative potential of the collector. The current is therefore confined in an area
controlled by the grid potential. As the transistor is in the on state, there is no barrier in all the area. The emitter-collector path through A position at the center and the path through B position (Figure 3.7(a)) near the edge of the opening have the potential profiles as the curves (x) and (y) in the Figure 3.7(b), respectively. Assuming that the collector current is roughly a superposition of the currents of many small diodes given by the paths through different positions, the small diodes at position A contributing to a high current (AON) and those at position B are just about to be turned on (BON), shown in the Figure 3.7(c). On the other hand, as the device is in the off state, the grid potential is positive and there is a potential barrier at the B position as the curve (z) in Figure 3.7(b), and the small diodes there is reverse biased (BOFF). As for A position, if it also has the potential profile like curve (z) in Figure 3.7(b), the off current comes from small diodes at position A will be small. However, if the potential profile is as the curve (y), there would be an undesirable leakage current from the barely-on small diode at A (AOFF). Theoretically an even more positive grid potential can drive it into curve (z). However in practice breakdown of the base/SIO/organic/collector diode may happen first.
2. C60 (N-type)
The grid control of the current can be further illustrated by looking at the spatial distribution of the current across the opening. For C60, some region near the center of the opening has positive potential for electrons to pass through. The effect of the grid near the edge is so significant that a potential barrier forms despite of the positive potential of the collector. The current is therefore confined in an area controlled by the grid potential. As the transistor is in the on state, there is no barrier in all the area.
The emitter-collector path through A position at the center and the path through B position (Figure 3.8(a)) near the edge of the opening have the potential profiles as the curves (x) and (y) in Figure 3.8(b), respectively. Assuming that the collector current is
roughly a superposition of the currents of many small diodes given by the paths through different positions, the small diodes at position A contributing to a high current (AON) and those at position B are just about to be turned on (BON), as indicated in Figure 3.8(c). On the other hand as the device is in the off state, the grid potential is negative and there is a potential barrier at the B position as the curve (z) in Figure 3.8(b), and the small diodes there is reverse biased (BOFF). As for A position, if it also has the potential profile like curve (z) in Figure 3.8(b), the off current comes from small diodes at position A will be small. However, if the potential profile is as the curve (y), there will be an undesirable leakage current from the barely-on small diode
roughly a superposition of the currents of many small diodes given by the paths through different positions, the small diodes at position A contributing to a high current (AON) and those at position B are just about to be turned on (BON), as indicated in Figure 3.8(c). On the other hand as the device is in the off state, the grid potential is negative and there is a potential barrier at the B position as the curve (z) in Figure 3.8(b), and the small diodes there is reverse biased (BOFF). As for A position, if it also has the potential profile like curve (z) in Figure 3.8(b), the off current comes from small diodes at position A will be small. However, if the potential profile is as the curve (y), there will be an undesirable leakage current from the barely-on small diode