Thesis Organization

This thesis is divided into four chapters. After a brief introduction given in Chapter 1, we describe the fabrication of the novel HC-TFTs device structure In Chapter 2. In addition, we also give a brief description about the DC stress definition and the degradation mechanism of DC stress in the same chapter. We conclude Chapter 2 by presenting and analyzing the results of the characteristics of HC-TFTs under various DC stress conditions.

In Chapter 3, we first give a brief description about the AC stress definition and the degradation mechanism of AC stress. Then we show and analyze the electrical characteristics of HC-TFTs under various AC stress conditions.

Finally, we summarize our conclusion and future work in Chapter 4.

Chapter 2

Device Fabrication and

HC-TFTs Under DC Stress

2.1 Experiment

． 2.1.1 Device Fabrication of HC-TFTs

In this study, the channel was prepared by solid-phase crystallization (SPC) method in which an amorphous Si deposited on oxidized Si wafers was annealed at 600 °C in N2 for 24 hours. A 35 nm-thick TEOS-oxide layer and a 200 nm-thick n⁺ poly-Si layer were then deposited and patterned as gate dielectric and gate electrode, respectively. S/D doping was formed by implanting phosphorous ions with a dosage of 5 × 10¹⁵ cm⁻³ at 45 keV. After standard processing steps, passivation, and metallization, the test structure further received a plasma treatment in NH3 ambient at 300 °C for 1 hour.

The top view of the test structure is shown in Fig. 1(a). The test structure is configured with four pairs of n⁺ electrodes at the edge of the channel. In Fig. 1(b), one pair of n⁺ electrodes is placed along the x (horizontal) direction to form the source and

In Fig. 1(c), the other three pairs are arranged along the y (vertical) direction to form three separate monitor transistors (MTs) to allow spatial characterization of the HC degradations along the channel of the test transistor after stressing. A common gate electrode shared by the test transistor as well as all three MTs is lying over the entire channel. Since each pair of n⁺ electrodes could be configured as the S/D of the respective MT, the current–voltage (I–V) characteristics of the corresponding MT could be characterized. The pair of S/D placed along the x-direction that serves to form the test transistor is subjected to HC stressing by applying a high voltage to its drain for inducing the HC degradations in the test transistor. According to their respective location relative to the channel of the test transistor, the three MTs are denoted as the source-side MT (S-MT), central MT (C-MT), and drain-side MT (D-MT), respectively. This unique configuration allows us to resolve the damage and identify the associated mechanisms at different locations along the channel of the test transistor after stressing. Important planar structural dimensions for the test structure characterized in this thesis are detailed in Fig. 1(a).

． 2.1.2 DC Stress Conditions

Fig. 2 shows the arrangement of the DC stress condition. The basic parameters of

DC signal consist of gate voltage (VG), drain voltage (VD), source voltage (VS), and stress time.

In this chapter, the static stress is used to degrade the HC-TFTs. The total stress time is 1000 sec.

2.2 Degradation Mechanism in Poly-Si TFTs under Static Stress

Fig. 3 depicts the hot-carrier degradation scheme of Poly-Si TFTs under DC stress.

As the impact ionization occurs near the drain site at high drain bias conditions, hot holes and electrons are generated. The injection efficiency into the gate oxide for hot holes and electrons depends on the vertical electric field near the drain and source.

The generated hot electrons release their energy inside the channel and at the oxide/channel interface, and could generate defect states and interface states, respectively. In the mean time, since no substrate contact is present in the TFT structure, hot holes generated by the impact ionization during hot-carrier stressing will drift toward the grounded source. Some of them with sufficient energy may surmount the barrier and be injected into the oxide.

2.3 Results and Discussion

Subthreshold characteristics of the lateral test transistor, as shown in Fig. 1(b), were measured before and after DC stress, and the results are shown and compared in Fig. 4. In Fig. 4(a), the test transistor was stressed under high bias of VG = 9 V and VD

= 18 V for 1000 sec to induce hot-carrier degradations. The degradations in device characteristics in terms of increased subthreshold swing and reduced on-current are indeed observed after DC stress, as can be seen in this figure. The post-stress ID–VG

shift is more significant when the lateral test transistor was measured at a low drain bias of VD = 0.1 V after DC stress. Furthermore, an increase in off-current could be detected at VD = 3 V and VG = −2 ~ −4 V. The above-mentioned observations are consistent with the well-known consensus that most of the damage events occur in the channel near the drain side of the test transistor. As a larger drain bias was applied during the measurements of subthreshold ID–VG characteristics, the depletion region near the drain side would extend. This phenomenon might in turn screen out more defects induced in the channel near the drain side, thus relieving the post-stress ID–VG

shift. Besides, it is well known that when the DC stress voltages are reduced, the degradation will also reduce. This is shown in Fig. 4(b) where the test transistor was stressed under lower biases of VG = 6.5 V and VD = 13 V for 1000 sec. The post-stress

ID–VG curve shows only a negligible shift relative to the fresh device under the milder stress condition.

The above-mentioned results of the conventional test transistor provide us the information about the major damage location in the stressed channel and the effect of stress voltages, as is well known in the literature. However, the detailed degradation mechanisms at different sections of the stressed channel could not be resolved by the conventional test structure. Moreover, the conventional test structure is also insensitive in detecting the induced damages while the applied stress voltages are low.

To resolve these shortcomings, the subthreshold characteristics of three separate monitor transistors (MTs) in the test structure were measured and the results are shown in Figs. 5 and 6. It is worth noting that the characteristics of the three MTs, as shown in Fig. 5, were measured using the same test structure with its test transistor DC-stressed and measured in Fig. 4(a). It can be seen that among the three MTs, the D-MT shows the worst degradation. Fig. 5(c) shows that the post-stress ID–VG shift is very significant even measured at a high VD bias of VD = 3 V. This phenomenon indicates that the induced traps are uniformly distributed along the entire channel of the D-MT. And this observation simultaneously confirms the inference drawn above in analyzing the results of Fig. 4(a). However, the remaining S-MT and C-MT exhibit some interesting results that are not explicitly revealed in Fig. 4(a). First, even though

not clearly distinguishable in Fig. 4(b), the C-MT indeed has a slightly degraded subthreshold swing when the measurement data are normalized. This implies that the generation of interface states at the oxide/channel interface is mainly responsible for the degradation. Second, the S-MT shows negative parallel shift in subthreshold characteristics, and this phenomenon indicates that positive hole trapping is preponderant in the oxide near the source side of the test transistor after DC stress.

These holes are generated by the impact ionization during the DC stress of the test transistor. Since no substrate contact is present in the TFT structure, these holes would tend to drift toward the grounded source, and some of them with sufficient energy might overcome the barrier and be injected into the oxide, causing positive hole trapping. Based on the results shown in Fig. 5, major degradation mechanisms occurred at different channel sections could be clearly distinguished and identified by the proposed novel test structure.

Fig. 6 shows the subthreshold characteristics of the MTs for the same test structure measured in Fig. 4(b) after stressing the test transistor under lower biases of VG = 6.5 V and VD = 13 V for 1000 sec. It can be seen that both S-MT and C-MT exhibit negligible shift in I–V curves after the stress, similar to the result of the test transistor, as shown in Fig. 4(b). By contrast, the D-MT shows obvious performance degradation after the stress. This phenomenon demonstrates the high sensitivity of the test

structure in detecting the hot carrier effects.

Chapter 3

HC-TFTs Under AC Stress

3.1 AC Stress Conditions

Fig. 7(b) shows the waveform of the AC signal. The basic parameters of AC signal consist of frequency (Freq.), signal high level (VG_high), signal low level (VG_low), high-level time (Thigh), low-level time (Tlow), rising time (Tr), falling time (Tf), and duty ratio.

Under AC stress, a pulse voltage is applied to the gate electrode by 8110A pulse generator, source is grounded and a high bias is applied to the drain, as shown in Fig.

7(a). Tr (rising time) is the time that voltage signal rises from 10% to 90% of the amplitude (VG_high – VG_low), while Tf (falling time) is the time that voltage signal falls from 90% to 10% of the amplitude (VG_high – VG_low). The total stress time is the summation of Thigh under the stress condition. The standard AC stress condition in the experiment is the gate voltage swing of 6.5 V to 0 V or 13 V to 0 V, the drain voltage of 13 V, frequency of 500 kHz, Tr and Tf of both 100 ns, duty ratio of 50%, and the total stressing time of 1000 sec. By changing these parameters, we can perform various stress conditions to test the reliability of HC-TFTs, and further

analyze the detailed degradation at different portions of the stressed channel by the new structure.

In this study, we first change the frequency from 100 kHz to 1000 kHz. Then, we change Tr from 100 ns to 10 ns. Finally, we change Tf from 100 ns to 10 ns.

3.2 Degradation Mechanism in Poly-Si TFTs under Dynamic Stress

Fig. 8 shows a schematic diagram for degradation model of the poly-Si TFTs under dynamic operation. When a high voltage is applied to the gate, the device turns on and is operating in ON state. The electrons gather to form a channel and the damage can be attributed to impact ionization stress, as shown in Fig. 8(a). In addition to the on-state hot-carrier degradation, the testers receive transient hot-carrier stressing when elections move rapidly from the inversion layer to the drain, as shown in Fig. 8(b). When the gate voltage falls, the electrons in the channel move rapidly to the drain, according to the Fermi energy level at the SiO2/poly-Si interface. In the case of a slow falling time, most electrons have enough time to be swept to the drain while the gate voltage falls from high to Vth. Thus, less electrons would be affected by the electric field at the channel/drain interface and less electrons are turned into hot

electrons to damage the drain side while the gate voltage falls from Vth to 0 V. In the case of a short falling time, more electrons do not have enough time to be swept to the drain while the gate voltage falls from high to Vth. They remain in the channel, taking into account the electron mobility in the channel, and are swept out while the gate voltage falls from Vth to 0 V. As mentioned above, the electric field at the channel poly-Si layer/drain interface becomes high, and the electrons gain energy from the electric field to become hot carriers. Therefore, more hot electrons are generated and cause traps in the grain boundaries near the drain regions in poly-Si in the latter case.

Since most of the generated trap states are located near the drain side of the test transistor, the degradation in HC-TFTs under dynamic stress can be easily detected by D-MT, as shown in Fig. 8(d).

3.3 Results and Disccusion

． 3.3.1 Frequency

The tester was first stressed under the stress conditions of VG_high = 6.5 V, VD = 13V, Freq. = 100 kHz, Tr = Tf = 100 ns, and duty ratio = 50%. Fig. 9 shows ID-VG

curves of TT, S-MT, C-MT and D-MT before and after 1000-sec AC stress, respectively. For Conventional TFTs, as shown in the ID-VG curve in Fig. 9(c), the

hot-carrier degradation is so minor and difficult to detect. In this study, we divide the channel into three parts, and measure the different portions of the channel as Figs.

9(a), (b), and (d) in order to resolve the degradation mechanisms occurred at these three different channel sections. In Figs. 9(a) and (b), S-MT and C-MT exhibit negligible degradation in the ID-VG curves after AC stress. However, in Fig. 9(d), D-MT shows a clear and obvious degradation in both subthreshold swing and ON current. As described previously in Chap 3.2 about the degradation mechanism under AC stress, most of the generated trap states are located near the drain side of the lateral TT, and can be easily detected by D-MT, as shown in Fig. 8(d).

Under the stress conditions of VG_high = 6.5 V, VD = 13V, Tr = Tf = 100 ns, and duty ratio = 50%, Figs. 9(c), 9(d) and 10(a), 10(b) show the ID-VG curves of TT and D-MT before and after 1000-sec AC stress under different frequency of 100 kHz and 1000 kHz, respectively. By comparing Figs. 9(c) and 10(a), though the case of 1000 kHz seems to be slightly worse, the difference in degradation between these two cases is very minor and the damaged location cannot be resolved without further examination. In contrast, the subthreshold characteristics of the D-MTs shown in Figs.

9(d) and 10(b) clearly indicate that an increase in stress frequency would lead to a higher degradation. In these figures, the on-state current and the subthreshold swing degradation are both observed under the AC stress. Since in these two cases, the total

time under VG_high is the same, the repetitions of the transient stages (Tr and Tf) are the reasonable cause of damage. According to the degradation mechanism under AC stress described in Chap 3.2, the single and major stressing parameter under AC stress is the transient hot-carrier stress. Thus, with higher frequency, more repetitions of the transient stress occur and lead to worse degradation.

Furthermore, the tester was stressed under another stress conditions of VG_high = 13 V and VD = 13V. Under the stress conditions of VG_high = 13 V, VD = 13V, Tr = Tf = 100 ns, and duty ratio = 50%, Figs. 11(a), 11(b) and 12(a), 12(b) show ID-VG curves of TT and D-MT before and after 1000-sec AC stress under different frequency of 100 kHz and 1000 kHz, respectively. The subthreshold characteristics of D-MTs shown in Figs. 11(b) and 12(b) clearly indicate that an increase in stress frequency would lead to a higher degradation, similar to the trend for D-MTs under the stress conditions of VG_high = 6.5 V, VD = 13V, as shown previously in shown in Figs. 9(d) and 10(b).

To further examine the effect of transient stage during stressing, the stress condition of VG_high = 13 V, VD = 13 V was performed. The characteristics of D-MTs under static and dynamic (Freq. = 100 kHz) stress conditions are shown in Figs. 13(a) and (b), respectively. It is seen that negligible degradation is observed for the former case, as can be seen in Fig. 13(a). This is reasonable since the voltage difference between the gate and drain electrodes is zero. Nevertheless, the degradation becomes

obvious as AC stress mode is applied. This provides a unambiguous evidence that the damage is incurred during the transient stages, with the aid of the novel test structure.

Figs. 14 and 15 show the on-current degradation and threshold voltage shift, respectively, of the TTs and all kinds of MTs under the stress conditions of VG_high = 6.5 V, VD = 13V, Tr = Tf = 100 ns, and duty ratio = 50%. By comparing the characteristics of C-MTs and S-MTs, the major damage location along the channel of the TT is unambiguously identified to be near the drain side. And, while the higher frequency is applied during stressing, the characteristics of D-MTs clearly exhibit worse degradation in on-current and more threshold voltage shift, as shown in Figs.

14 and 15. These results demonstrate the capability of the test structure in spatially resolving the damage location and its excellent sensitivity for detecting the frequency-dependent degradation.

． 3.3.2 Rising Time and Falling Time

The testers were stressed under the stress conditions of VG_high = 6.5 V, VD = 13V, Freq. = 500 kHz, and duty ratio = 50%. Figs. 16(a), 17(a) and 18(a) show the on-state current degradation, threshold voltage shift and subthreshold swing under 1000-sec AC stress with stable T = 100ns albeit different T, respectively. Figs. 16(a), 17(a) and

18(a) clearly show that the degradation of TT is mainly related to D-MT. This is because the testers receive transient hot-carrier stressing when electrons move rapidly from the inversion layer to the drain as the device is turned off quickly. While Tf

decreases, the testers receive much severe transient hot-carrier stressing with worse degradation, similar to the degradation mechanism under AC stress described previously in Chap 3.2. Thus, the major damage location along the channel of the TT is unambiguously identified to be near the drain side. And with the aid of the novel test structure, the results of the D-MTs in terms of on-state current degradation, threshold voltage shift and subthreshold swing under 1000-sec AC stress with stable Tr = 100ns, albeit different Tf, provide a clear and definite evidence.

Figs. 16(b), 17(b) and 18(b) show the on-state current degradation, threshold voltage shift and subthreshold swing under 1000-sec AC stress with stable Tf = 100ns but different Tr, respectively. As the test transistor with Tr = 20ns shows a strange trend in the on-state current degradation, threshold voltage shift and subthreshold swing, a solid line was used to fit the trend in this study, and will be re-visited in the future work. With the aid of the novel test structure, we note some interesting phenomena. First, TTs, S-MTs, C-MTs and D-MTs exhibit negligible shift in the on-state current with decreasing Tr, as shown in Fig. 16(b). Second, in Figs. 17(b) and 18(b), TTs, S-MTs and C-MTs also exhibit negligible threshold voltage shift and

subthreshold swing with decreasing Tr. In contrast, D-MTs show an obvious trend that larger threshold voltage shift and worse subthreshold swing degradation occur with shorter Tr. The reason for the above-mentioned phenomenon is still not clear at present, and will be studied in detail in the future.

Chapter 4 Conclusions

In this study, we have proposed and successfully demonstrated a new test structure suitable for monitoring the spatial hot-carrier degradation in poly-Si TFTs not previously possible. Our results indicate that this unique configuration is capable of resolving the spatial damage induced at different locations along the channel of the test transistor and, based on the observations, major mechanisms responsible for the resultant degradation could be identified. The new test structure is also shown to be highly sensitive for detecting degradations in even slightly damaged devices.

With the aid of this novel test structure, we can perform electrical characterization not possible with the conventional TFTs. Thus, new phenomena are waiting for us to unveil. In the future, we will further analyze the hot-carrier degradation of HC-TFTs under various stress conditions in detail. The new HC-TFTs thus allow us to gain a clear understanding of the model of the hot-carrier degradation mechanism under both static and dynamic stressing.

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