Thesis Organization - 語音系統低功率低失真三角積分數位類比轉換器

Chapter 1 Introduction

1.2 Thesis Organization

This thesis is organized into six chapters.

In Chapter 1, this thesis is briefly introduced.

Chapter 2 describes the considerations of the delta-sigma DAC. It includes the architectures of the interpolation filter and the delta-sigma modulator. Finally, the one-bit and the multibit quantizers are compared.

Chapter 3 describes the key circuit blocks used in delta-sigma DAC. Among them are the interpolation filter, the multibit delta-sigma digital modulator, the thermometer encoder, the data weighted averaging encoder, the multibit switched-capacitor DAC, and the RC lowpass filter. The simulation results and the algorithms of each block are also presented.

Chapter 4 introduces the implementation of the delta-sigma DAC in detail. The issues in the design of the digital part circuit are also indicated. Then the bootstrapped switch is implemented to reduce distortion. Finally, the layout of the analog part

Chapter 5 presents the testing environment, including the component circuits on the DUT (device under test) board and the instruments. Then, the analog circuit of the delta-sigma DAC is fabricated in a standard TSMC 0.18μm CMOS Mixed-Signal process and the pin configuration is listed. The measured results of this chip are also summarized.

Finally, the conclusions of this thesis are summarized in Chapter 6.

Chapter 2 General Design Consideration in Delta-Sigma D/A converter

2.1 Introduction of System Architecture

Delta-sigma DACs are preferred over Nyquist rate DACs in high resolution applications, because they relax the analog filter requirements. A simplified block diagram of an oversampled delta-sigma D/A converter is shown in Fig. 2.1 [3]. A digital signal with N-bit words is sampled with a data rate of fN. The interpolator achieves a higher rate by inserting 0’s between each input word with a rate of M fN

and then filtering by a digital lowpass filter.

Figure 2.1 Simplified block diagram of a delta-sigma DAC.

The 1-bit output signal of the digital delta-sigma modulator can be converted to an analog signal by switching between two reference voltages. This is followed by an analog lowpass filter to remove the high frequency quantization noise and yields the required analog output signal. The sources of error in the delta-sigma DAC are the device mismatch which causes harmonic distortion, rather than component noise, device nonlinearities, clock jitter sensitivity and inband quantization error from the

The signal spectra of the input signal and the interpolated signal are shown in the top two figures of Figure 2.2. The output signal of the interpolation filter is passed through a delta-sigma modulator, in which the digital bit stream is truncated into words with less number of bits and keeping the result quantization noise out of the signal band. Finally, the data is transferred into analog signal by a combination of DAC and lowpass filter. The DAC and the first stage of the lowpass filter are implemented by using a switched capacitor filter typically. The switched capacitor filter is followed by a continuous time lowpass filter to attenuate the quantization noise properly. The signal spectra at the input and output of the analog section are shown on the bottom two graphs of Figure 2.2.

Figure 2.2 Frequency spectra at different points of the delta-sigma DAC

2.2 Interpolation Filter

Figure 2.3 Block diagram of interpolator

A simplified block diagram of interpolator is shown in Figure 2.3. The digital input signal x(n) is upsampled to yE(n) by an oversampling ratio L. If the sampling rate of x(n) is a Nyquist rate fs, the sampling rate of yE(n) will be L fs. The Figure 2.4 shows the detail about how to increase sampling rate.

Figure 2.4 Spectra and waveforms of origin and upsampling signals

For example of oversampling ratio L = 2, the signal x(n) is converted into yE(n) by inserting one 0’s into each input signal. The top graph of Figure 2.4 shows the difference between input and output. An anti-image filter is necessary to filter out the undesired image signal shown in the bottom graph of Figure 2.4. The detail of anti-image filter is discussed in the following subsections.

2.2.1 Finite Impulse Response (FIR) Filter

The anti-image filter is used to filter out the undesired image signal caused by upsampling. One of the common realizations of anti-image filter is Finite Impulse Response (FIR) filter. Comparing to Infinite Impulse Response (IIR), the FIR filter is linear phase, stable and easy to implement. However, high order is necessary for a sharp cutoff FIR filter. Figure 2.5 shows the structure of FIR. The number of h[n-1]

means n-1 orders or taps.

Figure 2.5 FIR structure

2.2.2 FIR Half-Band Filter

The technique of half-band is efficient in reducing the circuit complexity in the design of a sharp cutoff FIR filter [4]. Because about 50 percent of the filter coefficients are zero, half-band filter can cut down the implement cost. First, denote the transfer function H(z) of a linear-phase, FIR half-band filter with order n-1

The filter is restricted the length N-1 is even. A half-band filter design trick is by transforming from a one-band linear-phase FIR filter. To design a one-band filter, the

specifications of ωp, ωs, and δ must be given, where ωp is passband edge, ωs is stopband edge and δ = δ1(passband ripple) + δ2(stopband ripple). Then we can design a (N-1)/2 order, one-band prototype linear-phase filter G(z) with specifications shown in Figure 2.6.

Figure 2.6 Amplitude response of G(z)

Its passband is from 0 to 2ωp and the transition is from 2ωp to π. Now we can

then H(z) is a half-band filter with specifications shown in Figure 2.7. The impulse response of H(z) is apparently related to that of G(z) by

where g(n) is the impulse response of G(z).

Figure 2.7 Typical amplitude response of a half-band FIR filter

Thus, the passband and stopband limit frequency must be located symmetrically, and the ripples must be the same in the two bands. These restrictions are usually adaptable in the interpolation-by-2 filtering.

2.3 Delta-Sigma Modulator

The delta-sigma modulator shown in Figure 2.8 is a negative feedback system [5].

It is the combination of oversampling technique and noise shaping function. The input bits are N and truncated into M bits by the quantizer in the forward path. However, a large quantization noise results from the truncation process. A high-pass transfer function affects the large quantization noise and shapes it into high frequency band.

Thus, most of the noise power resides in the high frequency spectrum outside the

signal band. This is what is called “noise shaping”.

Figure 2.8 The structure of delta-sigma modulator (interpolator structure)

2.3.1 Quantization Noise versus Oversampling

First, modeling a quantizer as adding quantization error e(n), as shown in Figure 2.9. The quantization error is the difference between input x(n) and output y(n). The linear model can be assumed that a uniformly distributed white noise is additive.

Figure 2.9 Quantizer and its linear model

Under the noise approximation, e(n) can be an independent random number uniformly distributed between ±Δ/2, where Δ is the difference between two adjacent quantization levels. Thus the quantization noise power equals Δ²/12 .The spectral density of the quantization noise Se(f) is shown in Figure 2.10. Se(f) is white and all its power is within ±fs /2. With a two-sided definition of power, the total noise power equals the area under Se(f) within ±fs /2. As the result of mathematics,

Figure 2.10 Assumed spectral density

If the desired signals are bandlimited to f0 and the sampling rate of signal is at fs, then an oversampling ratio (OSR) can be defined as OSR ≡ fs /2f0, where fs > 2f0. Since the signals of interest are all within ±f0 after quantization, y1(n) must be filtered by H(f) to create y2(n), as shown in Figure 2.11. This filter with transfer function H(f) eliminates quantization noise out of f0. The power within the signal y2(n) is still the same as the input signal, because we assumed that the signal-band is below f0. But the quantization noise power is reduced to

thus, we can decrease 50 percent of the quantization noise power or 3 dB, equivalently 0.5bits, by doubling OSR.

Figure 2.11 (a) A simple oversampling system. (b) The filter with brick-wall response.

Assuming the input signal is a sinusoidal wave, its maximum peak value without clipping is 2^N(Δ/2). For this sinusoidal wave, the signal power, Ps, equals to

then the maximum signal-to-noise ratio (SNR) can be calculated by the ratio of the signal power to the quantization noise power in the signal y2(n).

max

10log

6.02 1.76 10log( )

The first term is the improvement in SNR by the N-bit quantizer. As discussing before, the straight oversampling provides a SNR enhancement of 3 dB/octave, or equivalently 0.5 bits/octave.

2.3.2 Delta-Sigma Modulator with Noise Shaping

A linear model of a noise-shaped delta-sigma modulator is shown in Figure 2.12.

The quantization noise is indicated by E(z). By approximating the linear model as having two independent inputs, a signal transfer function, STF(z), and a noise transfer function, NTF(z), can be derived.

( ) ( )

When H(z) goes to infinity, NTF(z) will go to zero. The output signal can be expressed as the combination of the input signal and the quantization noise. In the frequency domain we can get

Y z ( ) = S

_TF

( ) ( ) z U z + N E z

_TF

( )

(2.11)

To noise-shape the quantization noise, H(z) must have a large magnitude from 0 to f0, which is the frequency band of interest. The signal transfer function, STF(z), approximates unity over the signal-band with the choice of H(z). Furthermore, the noise transfer function, NTF(z), approximates zero over the same band. Thus, the

quantization noise decreases while the signal is almost unaffected.

Figure 2.12 Linear model of the modulator

For the common case, the noise transfer function of a delta-sigma modulator must be a highpass function. Because the zeros of NTF(z) are equal the poles of H(z), we can get H(z) = 1/(z-1). Then the signal transfer function is given by

( ) 1/( 1)

We can find that the signal transfer function is simply a delay. If the order of the delta-sigma modulator is L, the noise transfer function is generally in the form of a discrete-time differentiator.

The examples of first-order and second-order noise-shaped modulators are shown in Figure 2.13. These modulator structures employ pure differentiation noise transfer functions. The dynamic range of the delta-sigma modulator can be derived with the order of the modulator L, the oversampling ratio R, the number of the quantizer

2 2 1 2

3 2 1

(2 1) 2

N L

DR L R

π +

⎛ ⎞

= ⎜ ⎝ ⎟ ⎠ −

(2.14)

Figure 2.13 Block diagram of pure differentiation modulators, (a) first order, and (b) second order.

Figure 2.14 shows the general shape of zero-order, first-order, and second-order noise-shaping curves. The noise power over the band of interest decreases as the noise-shaping order increases. However, there are some issues about increase of out-of-band noise and stability for the higher-order modulators.

Figure 2.14 Different orders of the noise-shaping transfer functions

2.3.3 High-Order Modulator

In general, an Lth-order noise-shaping modulator improves the signal-to-noise ratio (SNR) by 6L+3 dB/octave, or equivalently L+0.5 bits/octave. There are two approaches - interpolative and MASH - for realizing higher-order noise-shaping modulators. The interpolative structure, as shown in Figure 2.8, is typically a single high-order structure with feedback from the quantized signal. It is more suitable than the error-feedback structure, as shown in Figure 2.15, to analog implementations of modulators due to its reduced sensitivity.

Figure 2.15 The error-feedback structure of a general delta-sigma modulator

One of the first approaches for realizing higher-order interpolative modulators is using a filtering structure similar to a direct-form filter structure. However, a direct-form-type structure is sensitive to component variations, which can cause the zeros of the noise transfer function to move off the unit circle. In order to improve component variations, resonators can be used with a modified interpolative structure, as shown in Figure 2.16. The resonators in this structure are due to the feedback signals associated with f1 and f2. They result in the placement of zeros in the noise transfer function located over the frequency-of-interest band. This arrangement provides better dynamic range performance than placing all the zeros at dc.

Unfortunately, it is possible for modulators of order two or more to become unstable, especially when large input signals are given. If they go unstable, they may never return to stability even when the large input signals go away.

Figure 2.16 A block diagram of a fifth-order modulator

Another approach for realizing modulators, MSAH (Multi-stAge noise SHaping), is to use a cascade-type structure, where the overall higher-order modulator is constructed of using the lower-order ones. The advantage of this approach is that the lower-order modulators are more stable, and then the whole system should remain stable. The arrangement for using two first-order modulators to realize a second-order modulator is shown in Figure 2.17. The first section’s quantization error, e1(n), is

passed to another modulator and the outputs of two modulators are combined. In such a way, the first section’s quantization noise is removed. The output is left only with the second section’s quantization noise, which has been filtered twice because of two modulators. According to the straightforward linear analysis, we can get

2 1 2

( ) ( ) (1 )

( )

Y z = z U z

⁻

− − z

⁻

E z

(2.15)

Thus, a MASH approach has the advantage that higher-order noise filtering can be achieved by using lower-order modulators. The lower-order modulators are much less sensitive to instability as compared with an interpolative structure having a high order with a single feedback.

However, the MASH approach with a cascade of first-order stages is sensitive to finite opamp gain and mismatch between the analog and digital circuitry. These mismatches cause first-order noise to leak through from the first modulator, and then reduce dynamic range of the system. To improve this problem, the first stage is often chosen to be a higher-order modulator. Its leaking noise does not cause as a serious effect as it would if the first stage was first-order modulator. It is important to minimize errors due to the input-offset voltage caused by clock feedthrough or opamp input-offset voltages. An additional circuit design must be employed to reduce these effects in practical applications. Finally, the MASH approach results in the digital output signal, y(n), as a four-level signal because of the combination of the original two-level output signals. This four-level signal requires a linear four-level D/A converter in a D/A application.

Figure 2.17 A second-order MASH modulator using two first-order modulators

2.4 Comparison of One-bit and Multibit

The comparison of one-bit and multibit modulators is based on oversampling ratio, linearity, stability, and out-of-band quantization noise. The main advantage of one-bit modulator is inherently linear since it only need to produce two output levels and two points can define a straight line. However, the one-bit modulator with higher-order is easy to become unstable. A stable modulator is defined as one in which the input to the quantizer remains bounded and the quantization does not become overloaded. An overloaded quantizer means its input signal is over the quantizer’s normal range. It causes the quantization error to be greater than ±Δ/2. According to a general rule, keeping the peak frequency response gain of the noise transfer function, NTF(z), less than the amplitude 1.5. In mathematical terms,

| N

_TF

( e

^j^ω

) | 1.5 ≤

for 0≦ω≦π (2.16)

should be satisfied for a one-bit modulator. It often results in a stable modulator with

conforming to this stability criterion. Another disadvantage of one-bit modulator is to result in a large amount of out-of-band quantization noise, which must be significantly reduced by the analog circuit. Such a task requires relatively high-order analog filtering. It increases the difficulty in designing the analog filtering circuit.

A multibit modulator can provide the improvement in SNR. From the formula (2.8), SNR increases 6 dB with increasing one bit in the quantizer output. Therefore, a multibit modulator of a given order can achieve the target of dynamic range with less oversampling ratio than a one-bit modulator of the same order. In the application of higher-order modulators, a multibit modulator is also more stable than a one-bit modulator [6]. Additionally, the use of the multibit modulator can significantly reduce the large amount of out-of-band quantization noise and tolerate relaxed out-of-band filter specifications, but it must take care to ensure the multibit output of the modulator remains linear. The linearity of the multi-level output is limited by the mismatches in the components which are used to generate the analog levels. The diagram of step mismatches in the D/A converter is shown in Figure 2.18.

Figure 2.18 Illustration of step mismatch in the D/A converter

These step mismatches caused by component mismatches result in the distortion over the signal band, and then reduce the obtained SNDR (signal-to-noise plus distortion ratio). In order to solve the mismatch problem, various linearization techniques have been proposed, such as trimming and dynamic element matching (DEM). The trimming technique is practical for a D/A converter to enhance the matching property of identical components. It does not require extra circuits to reduce mismatch effect if each component is trimmed individually. However, trimming technique is expensive, time-consuming, and not a one-time process since device aging and temperature variation occurring in the lifetime of a D/A converter reduce the effect of compensating mismatches. The algorithm of DEM will be discussed in the following section.

Chapter 3 Design of Multibit Delta-Sigma D/A Converter

3.1 Multibit Delta-Sigma DAC Architecture

The four main architectural level parameters for a multibit delta-sigma DAC are oversampling ratio, noise-shaping order, quantization level, and reconstruction filter order [7], [8]. The design criteria for selecting these parameters will be discussed later.

The overall adopted architecture for the designed multibit delta-sigma DAC is shown in Figure 3.1. The resolution of the input signal is 18 bits. The input sampling rate, fs, is 44.1 kHz. It is interpolated by a 64× OSR (oversampling ratio). The resulting signal with 18 bits is passed through a third-order digital delta-sigma modulator. Here the operating speed is 2.8224 MHz because of the factor 64×. The multibit delta-sigma modulator generates a 15-level output.

Figure 3.1 Overall architecture of the multibit delta-sigma DAC

The drawback of a multibit delta-sigma modulator is the nonlinearity of the multibit digital-to-analog interface which is realized by a number of components, such as capacitors or resistors. The nonlinearity is due to the mismatch between the components. To improve the nonlinearity of the multibit modulator, a DEM algorithm can be adopted before passing the output of the multibit modulator to the analog reconstruction filter. How many bits used in the quantizer depends on the consideration of designing the analog circuit. The analog reconstruction filter is composed of a 15-level DAC and a first-order RC LPF (low-pass filter). The output signal of the digital circuit is transferred to the analog signal by a 15-level internal DAC, and then filtered by a first-order RC LPF.

3.2 Interpolation Filter

An interpolation filter is used to increase sampling rate of the data. Its purpose is to decrease the quantization noise and relax the out-of-band filtering specifications.

The higher OSR (oversampling ratio) is adopted, the better SNR is obtained and the out-of-band filter is easier to design. However, the high OSR increases circuitry speed requirements. It enables digital operation at high voltage and a corresponding increase in digital power consumption. On the contrary, the low OSR results in reduction in power consumption of the digital circuit but causes higher quantization noise.

Therefore, how to decide on an OSR is a tradeoff between factors in power dissipation, quantization noise, and requirements of the analog filter.

A block diagram of the whole interpolation filter is shown in Figure 3.2. The interpolation filter is composed of three stages and upsamples the 18-bit input data by 64× and eliminates baseband images around multiplies of sampling rate. The first two

stages of the interpolation filter are implemented by a 48-tap finite impulse response (FIR) filter and a 20-tap FIR filter. The final SINC filter with 8× interpolation is realized by a simple zero order hold register.

Figure 3.2 The block diagram of the interpolation filter

Their cutoff frequencies are half fs equally, which means the passband is signal

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