Thesis Organization - CMOS 低功率電流再利用壓控震盪器之研製

Chapter 1 Introduction

1.2 Thesis Organization

In chapter 2, the basic theory for the design of VCO application was described. Related methodology including general consideration in LC tank, Phase-Noise and MOS Varactor was used to design a reasonable VCO, as shown in Chapter 3 and 4 topologies, simulation, measurement and some important skills of design. Two VCO chips which using current-reused configuration with buffer for L-band and Wimax FWA frequency applications were finished. Related characteristics were also described in this chapter.

In chapter 4, the other structure for low power-consumption application with two balance resistors above N-P MOS drain node was introduced. The operating current can be reduced by half supply current and two drain resistors, which not only improve magnitude symmetry of output signals but also providing negative conductance. Related structures were compared in this chapter.

In chapter 5 will summarized all of this work.

Chapter 2 Basics of Voltage Controlled Oscillators

________________________________________________________

2.1 General Oscillators Considerations

This Oscillator was viewed as feedback circuits. It has a self-sustaining mechanism which noise to grow and become periodic signal. [2]

The feedback is circuits show in Figure2.1 It’s consideration of the simple linear feedback system depicted with the overall transfer function as following

( ) ( )

( ) 1 ( )

Y s H s

X s

H s

−

(2.1)

A self-sustaining mechanism arises at the frequency s0 if

H s =+1, and the oscillation

( )⁰ amplitude remains constant if s0 is purely imaginary，i.e.,

H s

( ⁰⁼

jw

⁰) =+1. The above rules are called Barkhausen’s criteria. Thus , according to the Barkhausen’s criteria，two conditions must be simultaneous met at ω0：

(1) the loop gain, H jw

(

⁰

)

,must be equal to unity.

(2) the total phase shift around the loop, H jw

(

⁰

)

, must be equal to zero (or 180° if the dc feedback is negative).

(a) (b)

Figure 2.1 (a) Feedback oscillatory system (b) Types of Frequency Selective network

The two port model in microwave theory is shown in Fig 2.1. Due to two-port network was closed feedback loop; generally we also can use one port equivalent circuit to discussion two port network oscillator illustrate in Fig 2.2:

Fig 2.2 One port view of oscillator

Generally frequency selective network had used LC tank resonator (LC tank oscillator)，the LC tank is shown in Figure 2.3 (a) and (b) with parasitic resistances.

(a) series^resonator (b) parallel circuit LC resonator Figure 2.3 LC resonator

The LC tank does not oscillate indefinitely because the resistor was dissipation stored

The Q is stored energy; X is of imaginary part, R is real part resistor. A real component sure includes some parasitic resistances. So we know the circuit hasn’t a finite Q. that will be influence Phase-Noise and Rp effect Oscillator condition.

2.1.1 Negative-Resistance Oscillator

In the idea of one-port model on feedback system, we can use negative resistance to reach oscillation. It is an active network generates an impedance equal to –Rp so that when the equivalent parallel resistance be Rp. Rp// (-Rp)= ∞ in this condition the tank oscillates indefinitely and allow steady oscillation.

This active circuit is replaced by a crossed-coupled pair which supplies the negative resistance to cancel out the energy loss due to the positive resistance of the LC tank. Figure 2.4 shows the schematic of the crossed-coupled pair and its small signal model. The negative impedance is derived as

Thus,

Figure 2.4 (a) Schematic of the crossed-coupled pair (b) Small signal model of (a)

2.1.2 LC Tank and Oscillator Conditions

In the LC oscillator circuits, LC tank determines main operation frequency condition.

Above negative resistance exposition LC oscillator include an active part to generate the negative resistance and a resonator network. And we know the operation frequency can be expressed as

f

π LC

= (2.7)

L and C can be series or parallel resonator show in Fig2.5 (a) (b), Ls and Lp represent integrated circuit inductance (also be lump component), Cs and Cp represent integrated circuit capacitance (also be lump component), Rx and GX represent the negative resistance and conductance generated by active part respectively. Rs and Rp represent the loses of the resonators.

(a) (b) Figure 2.5 (a) Series LC resonator (b) Parallel LC resonator

In above section introduce negative resistance, who to get oscillator. One port negative resistance oscillator show in Figure2.6 Zin=Rin+jXin (active device input impendence).

Usually the Zin should dependon bias voltage, current and frequency so, we can be expressed as [3] ,

Z

ⁱⁿ=( ,

I j ω

R I j

ⁱⁿ( ,

ω

jX I j

ⁱⁿ( ,

ω

) and load impendence expressed as ZL=RL+jXL

Figure2.6 One port oscillator circuit noise or signal can driver circuit in the LC oscillator operation frequency ω . When I increase some value makes

R I j

ⁱⁿ( ,

ω

0)+

R

^L= and0

X I j

ⁱⁿ( ,

ω

0)+

X

^L= , that oscillator 0 continuing stable.

However, it isn’t promises stable oscillator at all time, so we must be quantification Z become to

Z I s

^T( , )=

Z I s

ⁱⁿ( , )+

Z s

^L( ) using Taylor series:

0, 0 2 Q circuits to get high steady.

Designing a good Oscillator not only considers steady oscillate that has other consider just like voltage bias (operation point), but also maximum output power and noise.

2.2 MOS Varactor

In this thesis, we design VCO used MOS varactor that has much advantage that just like high turning rang and low phase-noise for VCO circuits than common PN junction varactor.

Generally VCO was used the p-n junction varactor or MOS varactor in LC tank. In this section we will study the MOS varactors operation mode in CMOS process [4].

2.2.1 MOS Varactors Operation Mode

Fig 2.7 Generally P-MOS cross section view structure

Fig 2.8 P-MOS C-V and operation mode

Figure 2.7 is shown the cross section view and capacitance V.S. voltage (C-V) of general P-MOS. Figure 2.8 is shown we connect D,S,B together and bias a variation voltage to get the result. Generally accumulation and inversion often used operation mode for vractor in VCO. We use three cases explanation which the operation mode, capacitor with bias voltage and C-V curve each other relationship.

Figure 2.9 Schematic of P-MOS Capacitor Circuits

Figure 2.10 Different Operation Mode of P-MOS C-V Curve

vdd

Case 1:DS=Vtune B=GND Case 2: DS=Vtune B=VDD

Case 3:DS=Vtune B=VDD Bias=0.8

In those cases, we had been used different bias voltage explanation that: Case 1: Using VD and VS to connect to Vturn, MOS and Body connect to ground which shown Figure 2.9 and the C-V curve is shown Figure 2.10, the case 1 is a normal operation mode that show capacitance increase form -5V to 5V,In the circuits application the Vturn was defined by maximum operation voltage . In here, we discuss 0-1.8V Voltage variation in all case.

The MOS capacitance value had been increased by Vtrun sweep when Voltage been increased which MOS’s depletion region also became to narrow at the same time. Following the depletion region narrow, the capacitance value will increase. In case 2, we connected Vbody to VDD =1.8V as shown in Figure 2.9 and Figure 2.10. The capacitance values were 5.5E-13 F and 4E-13 F reference at 0V in case 1 and 2 results respectively which enhance capacitance turning range that meaning can increase frequency turning range because the narrow speed of MOS depletion region is cause by the Vbody potential.

Last case, case 3: The case of fundamental purpose in simulation real VCO consideration at VG voltage. It has been reduced enhance capacitance of case 2 by VG

potential influence.

2.3 Phase Noise

The Phase-Noise is a very important parameter for VCO that is influencing down-converter or up-converter signal noise rate (SNR) in mixer. It will make signal interference RF transceivers normally working. General the noise generated main by the active devices but passive also make it that will include some active/passive noise to output signal.

Due to CMOS devices are a nonlinear component, which uses CMOS device to design circuits that will have nonlinear phenomenon. It makes noise voltage, AM/PM modulation current-noise and all nonlinear problems to include carrier signal.

The phase-noise was defined show in fig 2.11 and uses equation (2.13) to explain the conception of phase-noise formation. From (2.13) sample defends for phase-noise (

L

Δ ,

f

)

fig 2.11 Output power spectrum for VCO

that domain parameter Pout and

N Hz

(1 −

BW

)mean given some offset frequency fixed noise power. The ideal Oscillator that phase-noise should be -∞ .

we can refer above Fig 2.11 and define basic phase-noise equation below Equation2.13

(1 )

2.3.1 A Linear and Time-Invariant Phase-Noise Theory

But phase-noise should be more complex, We can follow phase-noise theory paper [5].

Get Equation 2.14. From Equation (2.14), The units is thus proportional to the log of a density. That are commonly expressed as “decibels below the dBc/Hz, specified at a particular offset frequency from the carrier frequency . For example, one oscillator center frequency at 1.5Ghz. we went to get phase noise at 100Khz or 1MHz as “-107 dBc/Hz at a 100kHz offset” and “-123 dBc/Hz at a 1MHz offset” respectively.

We can know Q factor one of do mainly effect phase-noise, the other Psig .If we hope get

good phase-noise performance, that can use High Q factor inductance (resonator) or

But Equation (2.14) can’t perfect expect phase-noise that show in figure 2.12 oblique line that don’t has consider Δ

ω

^{1 / f}³ corner. So we can use Leeson’s model. Equation (2.15) that included Δ

ω

^{1 / f}³ corner and it uses measurement results to fit and got this Leeson’s curve fit model. Although Δ

ω

^{1 / f}³ generates from 1/ f noise or is call as flicker noise by active devices (MOS…ect.) but how to transform and up-convert become Δ

ω

^{1 / f}³ region. Leeson law doesn’t have sensible exposition. The Linear time-invariant and phase-noise theory has been presented in 1966 by Leeson.

Equations (2.15) F is device excess noise number experience parameter, Q factor tell us Improve phase-noise the same above considers.

2.3.2 A Linear and Time-Varying Phase-Noise Theory

A Linear and Time-Varying Phase-Noise Theory considered impulse current inject to LC resonator that made phase and amplitude influence although influence reduce by time but phase change doesn’t restore by that. Show in fig 2.12 upper Fig inject a noise at π time, that waveform only changed amplitude no phase change, if inject noise at zero crossing point just like fig 2.12 lower Fig that no amplitude changed but waveform move front mean phase will be changed. Follow the increase time above change phenomenon, amplitude and phase both be changed. Therefore analyze oscillators’ noise injection used two theory to improve phase-noise phenomenon.

fig 2.13 phase be changed by impulse current versus time

Show fig 2.13 The signal transport phase and amplitude be influenced. Following

fig 2.14 The equivalent block diagram of the process

time we integration all signal and signal be modulated (PM) finally signal output. Among the signal transport follow

max

( )

i t

q

form thermal noise and active device (MOSFET) such as 1/ f

noise and Γ( )

ω

₀^t (ISF(Impulse Sensitivity Function)) generated by LC oscillator such as figure 2.14 theory that will changed LC oscillator output signal phase-noise and amplitude by injection noise. and all signal be integrated to ( )

φ t

Assume Equation (2.18) small amplitude disturbance get results in two equal-power sidebands symmetrically disposed about the carrier

( )

And using above result can derive the white noise source. The current of white noise source can be expressed as

From Parseval’s theorem

And sinusoid voltage (2.20) can get phase noise by white noise

( )

(2.21) tell us, that can enhance Q values and fit waveform (reduce Γ (ISF) value) to ²_rms improve phase-noise interference from white noise source.

And VCO inside 1/ f spectrum noise power density

be changed and changed phase quantity by noise or waveform.

Above section we know phase-noise formation that from noise injection and device inside 1/ f noise. We discuss figure 2.15 final step “phase-modulation”, the ^1/

( )

⁺

^ω

³^and

( )

1/ +

ω

corner frequency +

ω

1/ f3 can get equation by compare (2.22) and (2.25) that below equation

1 / 1 / 1 /

2 2 0

4 2

f f f dc

rms rms

ω ω C ω

^⎛ ^Γ ^⎞

Δ = ⋅ Γ = ⋅⎜⎝Γ ⎟⎠

(2.26)

fig 2.15 Evolution of phase-noise

The noise signal into circuit become phase-noise that from

c ,

₀

c ,

₁

c ,

₂

c by

₃

ω

₀, 2

ω

₀, 3

ω

0 integrate total signal and become phase-noise (middle Figure).and phase-modulation will signal up convert to

ω

₀.

Finally, In this theory gets good phase-noise performance that must reduce ^1/

( )

⁺

^ω

phase-noise and Δ

ω

^{1 / f}³ but it relate to

c (ISF DC).so we need have odd-symmetry (output

₀ waveform) to improve .the other way, active component noise (1/ f noise) we can use increase gm to reduce phase-noise but that will consume more power and increase voltage swing also need more current. So power- consumption trade-off between Q-factor, voltage swing and odd-symmetry waveform.

2.4 Voltage Controlled Oscillator (VCO)

The Voltage-Controlled-Oscillator (VCO) is provided signal to mixer up/down convert frequency supply Analog-digital convert (ADC or DAC) or antenna to transport relate signals and that also can be used on frequency divider, phase-locked loops, clock recovery circuits and frequency synthesizers.

In the VCO that have some important specification, like output power/power flat in turning voltages, turning range (different voltages different output frequency), Phase-noise (it’s very important spec. for VCO) and power-consumed. In different standards may need narrow channel spacing, low-Phase-noise and some designates request.

2.4.1 Basic Properties

Above section, we knew oscillator condition and how to oscillator. In this section we will introduction VCO spec. detail following below :

1. Pulling effect: In different (non-ideal load) of output impedance may made oscillator frequency variation. Usually uses VSWR (Voltage Standing Wave Ratio, equation (2.27)) by 1.5 to determine signal variation. In the real communication system, device operation may be on/off in any time and some operation mode, like saving mod that will made some on/off and changes output impedance that may have some frequency variation.

2. Pushing effect: The result of variation by power supply change that will change output frequency. The power supply be changed, the reason often come form share power source In the circuits. So we need a stable circuit make sure voltage change situation to be minimums.

3. Phase noise: An active device operation mode(gm), inductance Q-factor, output power amplitude, above parameter will effect phase-noise. A bad phase-noise would corrupt wanted signal in the receiver. we called reciprocal mixing.

4. Output power and harmonic rejection: we need to follow and consider communication system specification to determine how much output power we need to drive the next stage, that harmonic rejection means it is closed to a sinusoidal waveform and often need under -20dbm difference main frequency output power.

5. Turning range: the same of all parameter for communication request specification.

Every communication standards has immobile frequency just like WiMAX WSC (Wireless Communication Services) that has two band 2.305~2.320GHz and 2.345~2.360GHz.Reference relate standards to design be requests. Generally VCO uses capacitance and bias voltage to change frequency to request frequency band.

In next section, we will use sample methods and follow to introduce design of VCO.

2.4.2 Design of LC VCO Methods

Recently differential VCO topology be used in many paper that had two output signal phase difference 180 degree feature. In fig.2.16 inductance and capacitance can generate resonance frequency by equation (2.28)

Figure 2.16 Inductance and capacitance of resonance circuit

resonance 2

f

π LC

= (2.28)

We can follow (2.28) to get to want oscillator frequency. Usually we use the equation to determine our oscillator. But actuality VCO oscillator should be fixed to become equation (2.29). Due to MOS also like a capacitance structure that has some parasitic Capacitor and that will effect on resonance frequency. So we must consider MOS parasitic Capacitor to

L

C

But, real oscillation frequency we have defined to (2.30), that not only consideration Cmos but also CV var which real operation mode of VCO circuits. The CV var is MOS gate depletion capacitance by voltage VG potential.

(2.30)

Circuits Design Flow is shown in Figure 2.17 :

Figure 2.17 VCO Circuits Design Flow

First step, we must know what kind of characteristics are we need it, just like High output power, low phase-noise , high turning range and power consumption…etc. If we were determined structure, next step. Selecting right LC Tank that cause characteristics of VCO, generally inductance Q factor determine to the Phase-noise good or bad which selecting a High Q factor is important for low phase-noise and use LC component to select oscillation frequency. Usually inductance already be defined then determined capacitance and frequency turning range at operation frequency. Finally Buffer is using to DC-block and 50Ω matching for measurement instrument.

Active circuit structure

LC TANK

L-Q optimization C- turning range

Buffer

2.4.3 Design Follows of VCO

Figure 2.18 common design follows for RFIC. Generally we must know what kind of topology that will be used to designs VCO. Example: high output power, low phase-noise

Figure 2.18 Common VCO project design follows Consideration of VCO topology

Get design spec. and circuit goal. Use CAD software simulations (goal spec.)

Consideration of Circuits of PAD parasitic effect (circuit level)

Use Cadence Virtuoso layout and check DRC and LVS

Correct layout-rule. extract all parasitic of layout connect line and uses ADS computing that effect for circuits.(PEX)

Check Post- Simulation result data cover spec.?

Fabricate

NO

YES

(Goal spec.)

, wide turning range ...ect. Moreover circuits must be goal spec. and we design and simulate circuits uses by simulation software ADS.

This is important for RFIC. The Pad and layout lines parasitic effect often direct influence circuit performance. So about parasitic extract detail must be careful that has two methods to equivalent pad parasitical quantities: 1.uses equivalent circuit illustration Figure 2.19:

Fig 2.19 pad & bonding wire equivalent circuit

The values are appraised. Pad C≅ 60fF, R ≅ 250Ohm, L ≅ 2nH and parasitical-resistor about 10Ohm. 2: uses EM software (ADS Momentum, HFSS and IE3D) to extract pad layout 2-port S-parameter substitute circuit illustration Fig 2.20:

Bond wire

Pad

(a) (b)

Figure 2.20 (a) S-parameter of substitute circuit (b) extrication of pad layout

We substitute the circuits by employ EM software extract data s-parameter file SXP(X=1,23…) and run simulation again that has almost get real characteristic before fabrication.(because maybe have some manufacturing process inaccuracy),we say parasitical-

quantity maybe make circuit fail , so we usually incessant check S-parameters of layout lines whether it influence the origin (goal) circuit characteristic or not and do some fixes on circuits to keep circuit characteristic.

Chapter 3 Design of Low-Power Current-Reused CMOS VCO

In this chapter, we will introduce to design of low power VCO. Low phase-noise is very important for any wireless communication systems that want to get low phase-noise and low power. We need some circuits techniques reach it. In below section, we will introduce low power structure circuit and explain it what different to convention.

3.1 Induction of Low-Power Current-Reused VCO Structure

In mobile and portable communication equipment the supply voltage should be as low as possible. To increase equipment operating time, this shows how importance of low-power circuits. A voltage controlled oscillator (VCO) is an important block and among the blocks of any transceiver that applied in mobile and portable equipments.

Show Figure3.1,It is low-power VCO structure[6] that uses one current path improve on conventional VCO circuits and the two currents path by this way in generally can reduce half current costs in the circuits.

Figure 3.1 Schematic of the basic topology of current-reused Differential LC-VCO [6]

The VCO be used P-MOS and N-MOS transistors in the cross-connected pair. The P&N-MOS can be reduced by half supply current and the degeneration source resistors can reduce body effect and improve magnitude symmetry of output signals. Also it is only one current the core power-consumed will be controlled.

Figure 3.2 Shows N-PMOS cross pair large-signal equivalent circuits, left circuit is no resistance original circuit that will discuss this form here, middle circuit is first-half period equivalent circuit (when the voltage at node X is high and low) and two parasitic capacitances Cx=C/2+Cpx and Cy=C/2+Cpy respectively from P-NMOS. The first-half period

During the first half-period as shown in the Figure 3.2, the M1 and M2 are ON and the current flows from VDD through the turning inductor L to ground. During the second half-period, the M1 and M2 are off and the current flows in the opposite direction through the capacitors Cx and Cy. (Note that in the conventional differential VCO, the cross-connected transistors switch alternately, the P-N MOSFETs switch at the same time. During the first half-period of oscillation, the P-N MOSFETs operate in triode mode near the peak of the voltage swing.

Figure 3.2 N-PMOS cross pair large-signal equivalent circuit [6]

gmp gmn

G gmp gmn Rs gmp gmn

= − ⋅

+ + ⋅ ⋅ (3.1)

From Equation (3.1), Gn (negative conductance) of Figure 3.1 gmp(transconductance of PMOS) , gmn (transconductance of NMOS) and source resistor Rs.

3.2 Design of Low-Power Current-Reused VCO for L-Band System

The L-band application uses frequencies from 1GHz to 2GHz that covered some mobile broadcast band like T-DMB, DVB-H, GPS, Galileo and some cell-phone band likes WCDMA, so lower power-consumed device development is requested. In next section, we will show my circuits that not only use in L-band and the other circuit uses on new wireless application WiMAX.

3.3 VCO Simulation and Measurements for L-Band System

3.3.1 Design of Structure

In this chapter, all circuit uses current-reused topology that has low-current and saves Power, because the N-P MOS pair operates in triode region near the peak of the voltage

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