This thesis is organized into the following manner.
In chapter 1, a brief overview of poly-Si TFTs for various kinds of applications is introduced, and several popular laser crystallization technologies are described. Then,
RPI CV model of Poly-Si TFTs and the other background studies are discussed briefly.
Finally, the motivation of this work is expressed.
In chapter 2, detailed fabrication processes of ELA and SPC poly-Si TFTs are introduced, respectively. The measuring conditions are described concisely.
In chapter 3, the discussion is divided into three parts: First, the phenomena of the C-V and C-f curves are analyzed. Second, an equivalent circuit model is proposed to illustrate each effective capacitance and resistance. Moreover, the methods of the parameters extraction are explained. Finally, the fitting results of the proposed model are compared with the measured capacitance. Besides, the dependence of these parameters on gate bias is discussed.
In chapter 4, the conclusions are given including the physical mechanism of the proposed capacitance model and the explanation of the phenomenon of the frequency response.
Chapter 2
Experimental Procedures
2.1 The device fabrication process
In this experiment, typical top-gate, coplanar self-aligned poly-Si TFTs are fabricated by ELA method.
The schematic cross sectional view of these devices are shown in Fig.2-1-1, Fig.2-1-1(a) and Fig.2-1-1(b) are n-type with lightly doped drain (LDD) structure and p-type poly-Si TFTs, respectively; the fabrication process is described below.
First, buffer layer was deposited on the glass substrate to prevent the diffusion of impurities existing in the glass substrate from the silicon layer. Then, undoped 50 nm thick amorphous-Si layer were deposited on buffer layer. After that, amorphous-Si films were recrystallized by ELA method under several different laser energies; here, the laser energy densities are 340 mJ/cm2, 360 mJ/cm2, and 380 mJ/cm2, respectively.
The recrystallized poly-Si films were patterned into the active islands with different dimensions. Afterward, the gate insulator was deposited; a 50 nm-thick oxide layer was deposited on the poly-Si film, and then a 20 nm-thick nitride layer was deposited on the oxide layer. Next, phosphorus ions and boron ions were implanted to form the n+, n-, and p+ source/drain regions and these dopants were activated by thermal process. Finally, metal layer was deposited and then patterned for the source/drain and
gate regions as the metal pads.
In our experiment, we compared several C-V and C-f measurement results under three different ELA laser energies.
2.2 C-V and C-f measurement
In our experiment, HP4156 was applied to measure the current-gate voltage (ID-VG) in order to check the device performances. Besides, HP4284 was used to measure C-V under several frequencies which range from 10 kHz to 1 MHz. In addition, we also measured capacitance-frequency (C-f) by HP4194 in several gate voltages that are biased in the depletion region, and the measured frequencies were from1 kHz to 15 MHz.
Chapter 3
Results and Discussions
3.1 The observation of C-V and C-f curve
3.1.1 C-V curve analysis
As we could observe that the measured CG-DS-V curves gradually increase from turn-off region, depletion region, to turn-on region in Fig.3-1-1(a), and the frequency dispersion phenomenon appears in the depletion region shown in Fig.3-1-1(b). The laser energy density of ELA poly-Si TFTs is 380 mJ/cm2 which provides excellent device performance. Other measured C-V curves of different laser energy densities are also shown in Fig.3-1-2(a) and Fig.3-1-2(b), which are 360 mJ/cm2 and 340 mJ/cm2, respectively. The frequency dispersion phenomenon in the depletion region becomes more and more serious; it is because of the degradation of the poly silicon films under these laser conditions. Fig.3-1-3 is the images of Scanning Electron Microscope (SEM) which is capable of producing high-resolution images of poly silicon film surface. We find that the grains of poly silicon films in Fig.3-1-3(a) are more uniform and larger than that in Fig.3-1-3(b) and Fig.3-1-3(c). The trap response time listed in Table.1 is extracted while VG bias is in the middle of the depletion region. The dependence of activation energy extracted from ID-VG measurement on
VG is shown in Fig.3-1-4, where the dimension of these poly-Si TFTs are identical;
W/L = 600µm /6µm. The activation energies of these three different device which the laser energy densities are 340 mJ/cm2, 360 mJ/cm2, and 380 mJ/cm2 are about the same; 0.65 eV. As device turn on, activation energies decrease to zero. Here, we could observe that when the laser energy density is 380 mJ/cm2, the activation energy of the device decreases faster and more steeply than the other ones. In other words, the poly-Si film recrystallized in this condition which has larger and more uniform grains results in better film quality and fewer trap states for the carriers to fill compared to the other device recrystallized under 360 mJ/cm2 and 340 mJ/cm2. Fig.3-1-5 shows the method of trap density extraction presented by modified Levinson theory [18]; the gentler the curve is, the fewer trap charges the film contains. Therefore, Levinson theory also identifies that when the laser energy density is 380 mJ/cm2, poly-Si film has better quality than that recrystallized by the other two conditions. Fig.3-1-6 shows the C-f fitting curves based on our proposed capacitance model that will be mentioned later and the measured capacitance converted from C-V. Here, we suppose the phenomenon is mainly affected by the defects which are trapped in the bandgap trap states. Because of the response time of the carriers released from trap states to conduction are different in each gate bias; meanwhile, the frequency of ac signal is low enough for the carriers injected from source/drain to respond. Therefore, we
hardly observe the capacitance caused by the carriers that are capable of following the small ac signal from10 kHz to several hundred kHz. When frequency increases to 10 MHz as shown in Fig.3-1-7, which is ELA p-type poly-Si TFT with W/L=600µm /6µm.
the measured capacitance reduces dramatically and achieves a specific saturation value in the turn-on region. It’s because of the carriers provided from source/drain that are unable to penetrate into the whole intrinsic poly-Si channel which means the carriers only partially respond to the channel region near the source/drain region and beneath the gate oxide. Fig.3-1-8 shows the C-V curve of the device with channel length as 600 µm, the capacitance value degrades when the frequencies are from 100 kHz to 10 MHz. Comparing Fig.3-1-8 to Fig.3-1-7, the capacitance degradation
phenomenon of the device with channel length as 600 µm biased in the turn-on region becomes severer due to the carriers provided from source/drain merely respond to an effective small areas which are adjacent to the source/drain region. Fig.3-1-9 shows C-V curve of n-type poly-Si TFT with W/L=600µm /6µm and LDD structure; the LDD length is 0.75 µm. The capacitance degradation phenomenon in the turn-on region is not as severe as p-type one, but still decreases obviously as frequency increases to 10 MHz. We attribute the variation between n-type and p-type device to the differences of the mobility between electrons and holes; the effective mass of electron is about four times lighter than that of hole, therefore, electrons are more
capable of following the small ac signal under high frequency operation than holes such as to penetrate into the middle of the channel region and respond.
3.1.2 C-f curve analysis
The measured C-f curves of ELA p-type poly-Si TFT which dimension is W/L=600µm /6µm are shown in Fig.3-1-10. Here, the gate biases are within the depletion region. All the measured capacitances under these gate biases decrease slightly from 1 kHz to 1 MHz, respectively; then decrease drastically as the frequency increases over 1 MHz. The frequency of ac signal is too high for the carriers to inject from the source/drain region to respond to the whole channel. In other words, the reduced capacitance value is observed because the carriers are gradually incapable of following the small ac signal over 1 MHz. For that reason, we consider when the frequency increases around to 15 MHz, there must be an additional effect to reduce the measured capacitance, and this effect has to be taken into account especially in high frequency condition.
The same phenomenon also occurs in the device with channel length as 600 µm shown in Fig.3-1-11, but the capacitance decreases drastically in lower frequency which ranges roughly from 10 kHz to 100 kHz. We can observe that as frequency increases above 1 MHz, this device does not work due to it can’t sustain good
performance under high frequency operation. Fig.3-1-12 shows the C-f curve of n-type poly-Si TFT with W/L=600µm /6µm and LDD structure; the LDD length is 0.75 µm. Different from p-type poly-Si TFTs, the capacitance degradation phenomenon should be occurred above 15 MHz because we observe all the capacitance values biased in the depletion region keep decreasing but do not achieve small specific constants respectively. Therefore, the capacitance should be degraded as the frequency extends over 15 MHz, which corresponds to the supposition:
electrons are more capable of following the small ac signal under high frequency operation than holes. In other words, n-type poly-Si TFTs are more promising in high frequency operation than p-type ones due to higher carrier mobility.
3.2 The proposed equivalent circuit model
3.2.1 The capacitance equivalent circuit model of the Poly-Si TFT
A capacitance equivalent circuit model is proposed shown in Fig.3-2-1. The equivalent circuit shown in Fig.3-2-1(a) is adaptable for short channel device; on the other hand, the equivalent circuit shown in Fig.3-2-1(b) is complete model which also can be applied for long channel poly-Si TFTs. In the effective device capacitor, a highly resistive intrinsic poly-Si channel capacitance and resistance have to be considered in the model. Ci represents the geometric capacitance of the insulator layer
which the area is the product of device width and length; Rpoly and Cpoly are the characteristics resistance and capacitance of the carrier lateral flow in the channel, respectively. CD represents the capacitance of depletion. Ct and Rt are the capacitance and the resistance which result from the trap states in the depletion region and connect in parallel with CD. Cct and Rct are the capacitance and the resistance which result from the trap states in the channel. Here, the trap states are caused by interface defects, grain boundary defects, and intra-grain defects. Besides, the specific response time constant of charge trapped in the trap state is the multiplication of Rt and Ct, and is a function of gate bias due to the relative position from trap state level to conduction.
In the turn-off region, Ct is also neglected because carriers can be supplied neither from the heavily doped source/drain regions nor from the intrinsic poly-Si bulk. Therefore, there is no frequency response under the strong reverse gate bias. In addition, Cpoly is expected to be absent due to the intrinsic poly-Si bulk is fully depleted. Therefore, only a series combination of Ci and CD is regarded as the capacitance equivalent circuit.
In the turn-on region, because a large number of carriers are injected from the heavily doped source/drain regions and accumulated at the interface, the amount of charges that are trapped at all these trap states can be neglected in comparison to the amount of injected carriers in the turn-on operating conditions. Therefore, the reason
why only Ci is observed as the frequency swept below several hundred kHz in C-V and C-f measurements is the carriers form a thin, highly concentrated layer which acts like a capacitor plate equal in area to the gate. However, in the high frequency region which is nearly over 1 MHz, a series combination of Ci and Cpoly is expected to explain the decreasing measured capacitance due to resistance-capacitance (RC) time constant of poly-Si. In other words, the frequency is too high for the carriers to charge and discharge, hence, Rpoly and Cpoly are important parameters that should not be ignored under high frequency operating conditions.
In device depletion region, as we observed the C-f curve in Fig.3-1-5, Cpoly and Rpoly still affect the drastic degradation of measured capacitance in high frequency region, on the other hand, Ct and Rt should be considered in the equivalent circuit model especially when frequency ranges from 1 kHz to 1 MHz because the number of defect trapped charges is comparable to the number of mobile charges supplied by source/drain region in the intrinsic poly-Si channel. Hence, Ct and Rt that are in parallel with CD can describe why the measured capacitance has a subtle decrease roughly below 1 MHz. Consequently, the effective capacitance of the equivalent circuit model is given by:
(1)
, where
(2) (3)
(4) The capacitance depends strongly on the change of frequency in the turn-on region and the depletion region; here, we focus on the discussion of the frequency response in the depletion region, and the equations shown above indicate that capacitance is a function of frequency under the depletion operating conditions related to carrier lateral flow and trap response time.
3.2.2 Methods of device parameter extraction
In our studies which focus on the analysis in the depletion region, main parameters are extracted from C-f and conductance-frequency (G/f-f) curves. In low frequency region, the value of measured capacitance at 1 kHz is the value of Cp in series with Ci. Here CP is the summation of CD and Ct affected by frequency.
Therefore, Rt and Ct are the fitting parameters that we determine to describe the phenomenon of the slightly decreasing capacitance. In high frequency region, we regard the value of measured capacitance as Cpoly at 15 MHz. Besides, according to
1
equation (1), C1 calculated from the effective capacitance of Ci and CP, is larger than Cpoly at least by one order in the depletion region; hence Cpoly can be neglected, and Rpoly can be obtained by the peaks of the G/f-f curves shown in Fig.3-2-2 under different gate biases. Fig.3-2-2 shows the G/f-f curve of p-type poly-Si TFT with W/L=600µm /6µm biased under depletion region. In addition, the response time constant of the trap level is the product of Rt and Ct. Fig.3-2-3 shows the G/f-f curve of p-type poly-Si TFT with W/L=600µm /600µm, Rpoly under each gate bias is still obtained by the peak of the curve. However, the curve in the device with channel length as 600 µm is asymmetric, which is considered an envelope formed by two curves, and caused by the trap states in the channel. Therefore, Cct and Rct are the fitting parameters that we determine to describe the phenomenon of the lingeringly decreasing capacitance. Besides, the response time constant of the channel trap level is the product of Rct and Cct.
3.3 The fitting results and the dependence of parameters on gate bias
Fig.3-3-1 shows the curves fitted by the equivalent model and the measured data of ELA p-type poly-Si TFT which dimension is W/L=600µm /6µm under each gate bias. We can see this model for short channel device is very similar to the measured value. The dependence of Rpoly on gate bias is shown in Fig.3-3-2, as VG is biased
from the depletion region to the turn-on region, Rpoly decreases swiftly and almost reaches a specific constant value. The comparison of Rpoly under two different lengths is shown in Fig.3-3-3, a prominent difference in the depletion region near the turn-off region can be observed. Furthermore, under the same gate bias, Rpoly of longer channel length device is larger which means the carrier lateral flow response to the change of the channel length. The dependence of the trap response time which is the product of Rt and Ct on gate bias is shown in Fig.3-3-4. We can observe that the trap response time becomes faster as VG is biased from the depletion region to the turn-on region. In other words, the trap charges are easier to release from the trap level to conduction. Fig.3-3-5 shows the curves fitted by the equivalent model and the measured data of ELA p-type poly-Si TFT which dimension is W/L=600µm /600µm under each gate bias. This model for long channel device is still similar to the measured value. However, some deviations occur in smaller gate biases, such as -2.5 V, -3 V. It is because the value of Cp defined at 1 kHz is not correct; the accurate Cp should be calculated less than 1 kHz as the capacitances reach individually stable
values. Thus, lower measured frequency and less noise are required. Fig.3-3-6 shows the channel trap response time, similarly, τct is the product of Rt and Ct on gate bias.
We can observe that channel trap response time becomes faster as VG is biased from the depletion region to the turn-on region which corresponds to the tendency of τt.
Chapter 4 Conclusion
In this thesis, we studied capacitance model and its frequency response of poly-Si TFTs. We introduced a physically-based equivalent circuit to illustrate the dependence of capacitance on frequency and gate bias. Here, we focused on the depletion region due to the drastic frequency response. For device with channel length as 6 µm, the slight decrease in measured capacitance under low frequency condition which ranges from 1 kHz to about 1 MHz results from the defects existing in the poly-Si film. As frequency increases over 1 MHz, the ac signal is too high for the carriers to inject from the source/drain region to respond in the whole channel.
Therefore, the reduced capacitance can attribute to the influence of the characteristics resistance (Rpoly) and capacitance (Cpoly) of the carrier lateral flow in the channel area which are considered connecting in series with an effective capacitance; the effective capacitance is combined by the insulator capacitance and depletion capacitance in series connection. The fitting curves calculated using the proposed model explained the measured capacitance very well.
As a result of the dependence of carrier lateral flow on frequency, Rpoly extracted from G/f-f is an effective parameter to explain the degradation of capacitance under
high frequency operation.
As the device dimensions scaled down, the influence of the characteristics resistance and capacitance of the carrier lateral flow in the channel area is not obvious but still can not be neglected, especially under high frequency operating conditions.
On the contrary, Rpoly is affected by the long channel length because the carriers can not totally respond to the whole channel area under high frequency operation; thus,
Rpoly has much larger variation compared to the shorter channel one. We can observe that τt becomes faster as VG is biased from the depletion region to the turn-on region.
In other words, these trap charges are easier to release from the trap level to conduction.
In conclusion, the effects of defects, device dimension, gate bias and frequency are considered in the proposed capacitance model. With the proposed equivalent circuit, we can develop physically-based C-V model for LTPS TFTs to replace current empirical C-V model in SPICE tool.
References
[1] A. G. Lewis, I-W. Wu, T. Y. Huang, A. Chiang, and R. H. Bruce, “Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs,’’ in IEDM Tech. Dig., pp. 843-846, 1990
[1] A. G. Lewis, I-W. Wu, T. Y. Huang, A. Chiang, and R. H. Bruce, “Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs,’’ in IEDM Tech. Dig., pp. 843-846, 1990