Chapter 1: Introduction
1.3 Thesis organization
In this thesis, we applied the nano-technology to the electronic and biology fields. In chapter 2, research on nickel silicide process was demonstrated. Firstly, we investigated the effects of capping layers on formation and electrical properties of Ni-silicided junctions. We found that Ti-capped silicide sample exhibited poorer thermal stability in comparison with uncapped and TiN-capped sample due to a high-resistivity NiTiSi compound formed on the surface of Ti-capped samples, which resulted in the increase of silicide thickness and junction leakage problem. Next, the improvement of morphological stability of NiSi on Si/SiGe film was proposed.
Moreover, nickel silicide formed on the nano-sized line was also investigated. A model for the stress-confined grain growth and recrystallization is proposed to explain the improved properties of the poly-Si-buffered film.
In the second section, a nanocrystal memory by a novel sol-gel method was studied. In chapter 3, the mechanism of the nanocrystal formation at different annealing temperatures and solvent were investigated. We demonstrated the sol-gel
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film started to hase-changing property from 600°C annealing, and finally transformed into NCs at 900°C. As to the solvent effect, the morphology of the nanocrystals for precursors in ethanol system was isolated type, while was interconnected form in IPA system. Ethanol as preparation solvent formed a thinner sol-gel film for spinodal decomposition, and was benefit for formation of isolated nanocrystals. The ethanol system derived nanoscrystal memory demonstrated a large memory window (9.8 V) than IPA system (3.8 V) due to the isolated nanocrystals. Moreover, we proposed a Ti-based nanocrysals memory by utilizing the hot hole trapping to program. With the merits of high-density nanocrystals and hot hole trapping, this nanocrystal memory exhibited excellent electrical performance in terms of the large memory window, high data retention, exceptional endurance, and high program speed.
In the third section, the nanowire and nanobelt field effect transistor (FET) was fabricated for biosensing application. In chapter 4, a single crystalline silicon nanowire FET was fabricated for deoxyribonucleic acid (DNA) biosensing. We employed the BRAFV599E mutation gene, which correlates to the occurrence of cancers, as the target biomolecule.
In addition, a silicon nanobelt (NB) FET was also fabricated by using the local oxidation of silicon (LOCOS) process. This approach prevents the need for expensive lithography tools to define the nanoscale pattern. The NB FET was applied as the
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real-time, label-free screening of hepatocellular carcinoma (HCC). We detected alpha-fetoprotein (AFP), hepatitis B virus (HBV) DNA fragment, and solution pH, respectively, to prevent the false positive issue. This multiplex sensing of AFP, HBV, and the solution pH suggests that our direct, label-free, ultrasensitive biosensor with the microfluidic chip might be applicable as an HCC detector in real samples.
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Fig. 1-1 (a) Conventional photolithography procedure. This procedure separates into two steps, step 1 is the preparation of the mask, and step 2 is the application of the mask to manufacture replicas. (b) Typical bulk-/ film-machining method, the channel is created by etching trenches in the substrate wafer or, alternatively, in the film deposited on the substrate.
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Fig. 1-2 Schematic diagram of the bottom-up procedure. A chemical reaction brings together some molecular aggregate to small crystal, and the small crystals attract surroundings into a nano-particle.
Fig. 1-3 Sc
Fig. 1-4 Sc mis-aligme mis-aligme
chematic rep ent problem ent.
presentation m. (a) contac
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(a)
(b)
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Fig. 1-5 T with silic
Typical layo cide process
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device. (a) wwithout silicide process, and (b)
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Fig. 1-6 Evolution of the non-volatile memory.
Method
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Chapter 2
Research on nickel silicide process
2.1 Introduction
The self-aligned silicidation (SALICIDE) process is one of the critical techniques for ultra large scale integrated (ULSI) circuits, and is more emphasized as the device dimensions is towards nanometer scale. By using this technology, the contact resistance of silicide-Si interface at poly-Si gate and source/drain regions will be decreased, thereby increasing the driving current and the transconductance (Gm) of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices [1].
TiSi2 is widely used as the silicide material for several years [2]. However, it has been found that the transformation of TiSi2 from high resistivity C49 phase to low resistivity C54 phase is restricted by the linewidth, causing higher sheet resistance for lines narrower than 0.35 μm [3]. Neither CoSi2 nor NiSi has such linewidth dependence effects as observed in TiSi2 [4]. On the other hand, with the continuously decreasing junction depth, the silicide thickness is being shrunk to decrease silicon consumption at the expense of a higher sheet resistance [5,6]. For this reason, NiSi is being considered as a potential candidate for deep sub-100 nm devices because the
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same sheet resistance can be obtained with less Si consumption as compared to CoSi2
[7-9].
Although NiSi have many merits, there are obstacles to be overcame such as large junction leakage current and thermal stability related degradation. Moreover, the reaction between nickel silicide and poly-SiGe is unstable. For these reasons, the improvement of nickel silicide process was demonstrated in this chapter.
2.2 Study on the capping layer for the formation of nickel silicide
junctions
In this section, we demonstrated the effects of the Ti or TiN-capped layers on thermal stabilities of nickel silicide thin film. One of the reasons of nickel silicide thermal stability is because the oxidized of nickel, results in the increase of silicide resistivity. Therefore, a capping layer on top of nickel thin film is necessary to prevent oxidant. Here we used various capping layers and compared their thermal stabilities.
The results showed that there was higher leakage current for NiSi sample with the Ti-capped layer than that of the uncapped layer. Further studies identified that the excess junction leakage current was due to the Ti-Ni-Si compounds layer formed on the nickel silicide surface.
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2.2.1 Experiments
The n+-p junctions were formed by As+ implantation at an energy of 20 keV with a dose of 5×1015 cm-2 followed by the rapid thermal annealing (RTA) process.
After wafers were cleaned, they were introduced to a cluster sputtering system to deposit the metal films. Prior to the film deposition, Ar presputter cleaning was further carried out to remove the thin native oxide layer. Ni films of 20 nm and Ti or TiN films were sputtered, respectively. The thickness of Ti thin film was 10 or 30 nm, and the TiN thin film was 30 nm.
After deposition of metal films, nickel silicidation was done in a RTA (AG 610) system, followed by a H2SO4 + H2O2 mixture to selectively remove the unreacted metal. Finally, TiN /AlSiCu /TiN was deposited and patterned as the metal pad. For easy identification, the uncapped silicide sample, Ti 10 nm-capped silicide sample, Ti 30 nm-capped silicide sample, and TiN 30 nm-capped silicide sample are denoted herein as uncapped, Ti 10-capped, Ti 30-capped, and TiN 30-capped, respectively.
The leakage currents of junction diodes were determined at a reverse bias of 5V by a HP4156 semiconductor parameter analyzer. For the unpatterend sample, sheet resistance of the silicide film was measured by a four-point probe.
Microstructures of the silicide films and interfaces were examined using transmission electron microscopy (TEM). The compositions and the phase identification of silicide films were carried out by energy dispersive spectroscopy (EDS) and x-ray diffraction
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(XRD) analysis, respectively. Compositional depth profiles were characterized by secondary ion mass spectroscopy (SIMS).
2.2.2 Results and discussion
Fig. 2.1 compares the sheet resistance of Ni silicide using different capping layer processes after annealing at 300-800oC for 30 sec in an N2 ambient. At temperatures below 450oC, all samples exhibit large sheet resistance and it is attributed to the formation of nickel-rich Ni2Si phase, as analyzed in XRD spectra of Fig. 2.2. NiSi with low sheet resistance (about 4~5 Ω/) are shown for temperatures ranging from 450 up to 600oC. At higher than 600oC, the silicide thin films start to degrade with slight increase in sheet resistance, especially for the Ti-capped samples, as shown in the inset of Fig. 2.1. The degradation for nickel silicide film annealed at higher temperature is attributed to either the phase transformation from low-resistivity NiSi to high-resistivity NiSi2 or the agglomeration of the silicide film caused by local energy equilibrium at the intersection of grain boundaries [10].
So far as the result of sheet resistance is concerned, the uncapped and TiN 30-capped samples exhibit better thermal stability than the Ti 10-capped and Ti 30-capped samples. Obviously, it does not conduce to relevant shift of the Ni-silicided transformation temperature by using either Ti or TiN capping layer on Ni-silicidation process. This result is distinct from the phenomenon of Co-silicidation process. It has been demonstrated that the transformation point of Co2Si to CoSi was shifted towards lower temperature by a Ti capping layer, which is arose from that the Ti capping layer lowers the activation energy for CoSi formation by eliminating the formation of SiO2
between the growing CoSi and the Co [11]. The fact that Ti capping layer does not
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play an active role for Ni silicidation process is ascribed to the lower reaction temperatures for Ni and Si.
The XRD spectra for samples annealed at 400, 450, 600 and 700oC are shown in Figs. 2.2 (a)-(d). All samples annealed at 400oC exhibit nickel-rich Ni2Si preferred orientation. After 450oC annealing, the NiSi phase predominated, and no NiSi2 phase was detected even the annealing temperature is up to 800oC (not shown here). This finding is consistent with the sheet resistance result that Ti-capped sample does not lead to a significant shift of the nickel silicide transformation temperature. It is more noteworthy that there are two peaks (about 40.6 and 43.3 degree) detected from the Ti 30-capped and Ti 10-capped samples (peaks from Ti 10-capped sample are unapparent, but still visible), while the uncapped and TiN 30-capped samples are not.
The intensity of the two peaks that were detected from the Ti 10-capped and Ti 30-capped samples increase with increasing either the annealing temperature or the Ti thickness, which indicate that there may be a Ti-compound layer formed on silicide thin film.
To verify the composition of the Ti-compound layer, samples were further analyzed by TEM. Figs 2.3 (a)-(f) show the cross-sectional TEM images of the uncapped, TiN 30-capped, Ti 5-capped, Ti 10-capped, Ti 20-capped, and Ti 30-capped samples annealed at 650oC for 30 s, respectively. As shown in the figures, there are two layers formed on the Ti 5-capped, Ti 10-capped, Ti 20-capped and Ti
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30-capped sample, while only a single layer are found on the uncapped and TiN 30-capped samples. For the Ti-capped samples, the thickness of the upper layer increased upon increasing the thickness of Ti capping. The two layers formed on the Ti 30-capped sample were also analyzed by EDS to confirm their compositions.
Figures 2.4a and b show the EDS analyses of the upper layer and the lower layer formed on the Ti 30-capped sample, respectively. It is clearly seen that the upper layer is composed of a high-resistivity NixTiySiz compound and could not be removed by etchant, while the lower layer is a relatively low-resistivity Ni-Si compound. Oxygen signal was not detected at either upper layer or lower layer in TEM and EDS results, which is distinct from the result of the previous report about CoSi2 study. It was reported that a Ti cap or alloying layer is capable of gettering oxygen that is incorporated into the deposited Co, and reducing interfacial oxide in the silicidation process by forming a TiO2 layer in the silicide surface [12]. The similar results are also found in the NiSi studies [13-14]. No detectable oxygen in this study is possibly due to the pre-etching process so that native oxide was completely removed and a clean surface was showed up to form silicide. Furthermore, it is found from Figs. 2.3b and 2.3c that the overall thickness of the silicide layers, as well as the NixTiySiz layer, increase with increasing the Ti capping layer thickness. This result is harmful to the electrical properties of the Ni silicided device because both thinner silicide layer and
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lower sheet resistance are the main demand for the ULSI technology. The thicker silicide layer will cause excessive leakage current of the source/drain region, and result in degradation in properties of the devices.
Fig. 2.5 illustrates the cumulative distributions of reverse-biased leakage current densities (JR) for the Ni-silicided n+-p junction diodes annealed at 500oC for 30 sec. Twenty five randomly chosen diodes of area 0.1 × 0.1 cm2 was measured at room temperature. As shown in Fig. 2.5, the uncapped and TiN 30-capped samples exhibit smaller leakage current densities than that of the Ti 10-capped and Ti 30-capped samples. As mentioned above, the thickness of NiSi and NixTiySiz layers increase with increasing the Ti capping layer thickness, as shown in the TEM images of Fig. 2.3. This means that increasing the Ti capping layer thickness result in the more seriously consumed junction depth, and hence, caused larger junction leakage current.
Fig. 2.6 reveals the SIMS depth profiles of As+ for samples annealed at 500
oC for 30 sec. There are almost the same junction depth for the uncapped, Ti 10-capped, and TiN 30-capped samples (about 0.076 μm at 1019 atoms/cm3). However, the As profile of the Ti 30-capped sample is shifted toward deeper side (about 0.091μm at 1019 atoms/cm3). This finding explains why the leakage current of the Ti 30-capped sample is slightly smaller than that of the Ti 10-capped sample shown in
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Fig. 2.5. It has been demonstrated that As is depleted in the TiSi2 layer and thus diffuses significantly into Si underneath [15]. Therefore, the Ti 30-capped sample with a thicker NixTiySiz compound layer, caused the impurity redistribution to induce a deeper junction depth. In addition, the “snowplough” effect that As accumulates at the silicide/Si interface, especially for the Ti 10-capped and Ti 30-capped samples, is found. This observation indicates that the Ti capping layer leads to the snowplough effect enhancement during the NiSi formation. Moreover, the accumulation of As is deeper for the Ti-capped sample, which is due to the formation of the thicker silicide layers, as shown in Fig. 2.3.
2.3 Study on morphological stability of the nickel silicide formed on polycrystalline Si/SiGe substrate
In this section, the stress-induced morphology and fine-line stability enhancement of NiSi on poly-SiGe with a buffer poly-Si interlayer was studied.
Polycrystalline silicon-germanium (poly-SiGe) is a suitable candidate material for replacing polycrystalline silicon (poly-Si) at the gate electrode because of its lower dopant activation energy, higher carrier mobility [16-17], and good compatibility with standard silicon CMOS processing technologies, as well as the possibility of tuning its work function merely by changing the mole fraction of Ge [18]. In addition, poly-SiGe films can be deposited at temperatures lower than those required for
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poly-Si films, presumably because of the lower binding energies of the Si–Ge and Ge–Ge bonds in poly-SiGe films relative to those of the Si–Si bonds in poly-Si films [19]. Unfortunately, combining nickel silicide processing with poly-SiGe materials suffers from the drawback that the direct reaction between nickel and poly-SiGe provides materials exhibiting relatively poor morphological stability relative to those obtained from poly-Si [20] because the melting point of the ternary alloy Ni(Si,Ge) is lower than that of NiSi. This problem restricts the further application of nickel silicide and poly-SiGe gate materials.
Here we compare the morphological stabilities and fine-line effects of
Ni/poly-Si/SiO2/Si-substrate, Ni/poly-SiGe/SiO2/Si-substrate, and Ni/poly-Si/poly-SiGe/SiO2/Si-substrate systems. We studied the effects of the
silicidation temperature on the sheet resistance of various films. In addition, we examined the fine-line effects of nickel (germano) silicided narrow lines. Although it has been reported that the resistance of NiSi formed on poly-Si lines exhibits independent geometrical dimensions [21], no literature exists describing the electrical properties of Ni(Si,Ge) formed on narrow poly-SiGe lines. Thus, we evaluated the morphology and recrystallization effects of these films, and propose a model that accounts for the stress-induced grain growth suppression and recrystallization effects.
2.3.1 Experiments
These experiments employed 6-inch (100)-oriented silicon wafers. A 500-nm-thick silicon oxide film was first formed, followed by the deposition of a (1)
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200-nm poly-Si film, (2) 200-nm poly-SiGe layer, or (3) 40-nm poly-Si/160 nm poly-SiGe stack layer. After RCA standard cleaning, 10-nm Ni and 4-nm TiN films were deposited through dc sputtering. After metal deposition, the Ni-silicidation reaction was performed in a rapid thermal annealing (RTA) system. Finally, a mixture of H2SO4 and H2O2 (3:1) was used to selectively remove the unreacted metal at a temperature of 120 °C. The sheet resistance of the silicide film was determined using a four-point probe system. A bridge structure was used in conjunction with an Agilent 4156A semiconductor analyzer to characterize the values of resistance of various narrow lines. The morphology of the film was examined using transmission electron microscopy (TEM). The stresses of these films were measured using a Tencor FLX-2320 instrument.
2.3.2 Results and discussion
After performing the silicidation reaction, the stacked (1) Ni/poly-Si/SiO2/Si-substrate, (2) Ni/poly-SiGe/SiO2/Si-substrate, and (3) Ni/poly-Si/poly-SiGe/SiO2/Si-substrate films were transformed into (i) NiSi/poly-Si/SiO2/Si-sub, (ii) Ni(Si1-xGex)/poly-SiGe/SiO2/Si-sub, and (iii) NiSi/poly-SiGe/SiO2/Si-sub species, respectively. The phase for sample (iii) was identified to be NiSi by XRD, since the thickness ratio of buffer poly-Si to Ni was close to the consumption ratio for forming the low-resistivity NiSi. Fig. 2.7 provides a comparison of the sheet resistances of these films as a function of the annealing temperature. The sheet resistances of samples (i) and (ii) increased slightly upon
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increasing the annealing temperature over the range 500–800 °C, and then increased abruptly at temperatures higher than 850 °C. In contrast, the resistance of sample (iii) remained constant after annealing at temperatures between 500 and 850 °C. This observation suggests that the insertion of the buffer film (i.e., poly-Si) between the Ni and poly-SiGe films was beneficial to the electrical and thermal properties.
Fig. 2.8 displays the sheet resistances of various narrow lines of samples (i)–(iii) annealed at 600 °C. The sheet resistance of lines of sample (i) remained nearly constant for line widths ranging from 200 to 100 nm, which is consistent with previous findings [22]. The slight decrease in resistance that occurred after shrinking the line width from 100 to 60 nm was caused by edge effects of the recessed spacer forming a thicker silicide at the line’s edge [23]. In contrast, the sheet resistance for sample (ii) increased upon reducing the line width. This phenomenon, the well-known fine-line effect, had been reported from a study of Ti silicide [24], but has never been reported for Ni(Si,Ge) lines formed on poly-SiGe. The fine-line effect vanished after insertion of poly-Si, i.e., for sample (iii). This behavior should improve the process stability of such systems, especially for sub-100-nm devices. We infer that the larger Ni(Si,Ge) grains resulting from the ready grain growth of poly-SiGe after annealing was the main cause of the increased sheet resistance in sample (ii). Similar behavior resulting from grain size effects has been described previously [25].
Fig. 2.8 displays the sheet resistances of various narrow lines of samples (i)–(iii) annealed at 600 °C. The sheet resistance of lines of sample (i) remained nearly constant for line widths ranging from 200 to 100 nm, which is consistent with previous findings [22]. The slight decrease in resistance that occurred after shrinking the line width from 100 to 60 nm was caused by edge effects of the recessed spacer forming a thicker silicide at the line’s edge [23]. In contrast, the sheet resistance for sample (ii) increased upon reducing the line width. This phenomenon, the well-known fine-line effect, had been reported from a study of Ti silicide [24], but has never been reported for Ni(Si,Ge) lines formed on poly-SiGe. The fine-line effect vanished after insertion of poly-Si, i.e., for sample (iii). This behavior should improve the process stability of such systems, especially for sub-100-nm devices. We infer that the larger Ni(Si,Ge) grains resulting from the ready grain growth of poly-SiGe after annealing was the main cause of the increased sheet resistance in sample (ii). Similar behavior resulting from grain size effects has been described previously [25].