When clustering stage is completed, each node (cluster) contains a hierarchical set of electrical pins. However, clustering only determines routing order of electrical pins, the actual routing path that connects all of the electrical pins is still undeter-mined. To increase routing success rate, each grid is updated with an offset cost such that router is discouraged to use valuable routing resources during routing stage.
g(x, y) = X
∀j,covers(x,y)
β
pwidth(OBB2 j)2+ height(OBBj)2 (3.1) Given a set of unconnected electrical pins, it is first decomposed to a set of
two-the bounding box. The offset grid cost is defined in Eq. 3.1. β is an empirical value to adjust the quality between detour wirelength and routability.
Fig. 3.6 illustrates an example using testcase amino-acid-1 that how adding offset grid cost can prevent failure. In Fig. 3.6(a), routing failure occurred since electrical pins are routed disregarding of the congestion. By adding offset grid cost, routing path will detour away from congested region and create room for inner electrical pins to escape, as illustrated in Fig. 3.6(b). Fig. 3.7 plot the tradeoff curve between reduction in number of activation sequences and total routed wirelegnth in response to different adjustment of β. Total routed wirelength increases steadily with increase in β. The response in reduction in activation sequences is a more delicate issue. Slight increase in detour creates room in congested region and enables more reductions in activation sequences. However, over-powering β creates undesired routing blockage which reduces number of reductions.
Figure 3.3: Bounding box estimation. (a) Using minimum distance to determine merging priority. (b) Bounding boxes for each edge. (c) Area of overlapping bound-ing boxes for net A. (d) Area of overlappbound-ing boundbound-ing boxes for net B. (e) Area of overlapping bounding boxes for net C. (f) Using area of overlapping bounding boxes as edge cost. (g) Using area of overlapping bounding boxes to determine merging priority.
Figure 3.4: Comparison in routed wirelength using area and diagonal of overlapping bounding boxes as edge cost.
(a) Area of OBB vs. diagonal length of OBB (b) HPWL of OBB vs. diagonal length of OBB
(c) Distance between two electrical pins vs. di-agonal length of OBB
Figure 3.5: Comparison in tradeoff between reduction in number of activation se-quences versus total routed wirelength.
(a) Routing result without offset grid cost.
(b) Routing result with offset grid cost.
Figure 3.6: Impact on routability with offset grid cost using testcase amino-acid-1.
Wires are detoured away from potentially congested region. (a) is a unroutable design and (b) is a routable design.
(a) (b)
Figure 3.7: Impact on detour wirelength and reduction in number of activation sequences with different adjustment of β in testcase amino-acid-1.
Chapter 4
Multi-Source Multi-Sink ILP Escape Routing
When all electrical pins are connected, the upcoming task is to route connected electrical pins to any peripheral electrical pad. The challenge is to route every merged electrical pins to an electrical pad using minimal routed wirelength. The multi-source multi-sink escape routing problem can be optimally solved by formu-lating it as an ILP problem. The notations used in the ILP formulation are defined as follows:
• pk denotes a pin k
• nj denotes a net j
• f(u, v) denotes flow from pu, a positive value means an outward flow and negative value means an inward flow.
The ILP formulation for multi-source multi-sink escape routing problem for pin-constrained EWOD chip is formulated as follows. Given a set of nets N = {n1, n2, ..., nj}, a set of edges E = {e1, e2, ..., ei}, a set of electrical pins P = {p1, p2, ..., pk} and a set of control pads B = {b1, b2, ..., bm}, minimize total flow for all pins in P .
The objective function is described in Eq. 4.1. Minimizing total flow value is equivalent to minimizing total escape route wirelength.
minX
Eq. 4.2 defines the conservation of flow. For a given electrical pin that is neither a source or sink, inward flow must equal to its outward flow. Eq. 4.3 defines the net flow for a given net nj must equal to 1. In graph representation, every electrical pin for a given net is connected to a super source and each net has an initial flow value equal to 1. Control pads can be regarded as sink nodes and all are connected to a super sink node. Eq. 4.3 defines the initial value such that every net can only have exactly one path escape to boundary electrical pad.
Eq. 4.4 defines terminating condition. When the summation value of flow for every electrical pad equals to the total number of nets, it represents that every net
can be crossed by defining that the absolute value of flow for any given electrical pin is less than or equal to 2. Eq. 4.6 defines the capacity constraint such that the absolute value of flow between any two electrical pins is less than or equal to 1.
Solving the ILP constraints traverses through all possible routing solutions. To accelerate runtime, a maze router is implemented to accelerate run time in exchange for less reduction in activation sequences.
Figure 4.1: Network and routing procedure for ILP formulation. (a) Network-flow for net A. (b) Set net A’s around flow equal to 1. (c) In-flow equal to out-flow to pass through flow to boundary. (d) Stop until boundary in-flow equal to total net number.
Chapter 5
Experimental Result
Table 5.1: Comparison with Prior Works [8] on Wire-Length and Pin Counts With-out Obstacles
[8] Our(Maze-Based) Our(ILP-Based) Direct Addressing [5]
benchmarks Chip Size #E #Pin #WL CPU Time(s) #Pin #WL CPU Time(s) #Pin #WL CPU Time(s) #Pin #WL CPU Time(s)
amino-acid-1 6X8 20 9 190 0.08 7 185 0 7 185 0.24 20 136 0.24
amino-acid-2 8X8 24 11 207 0.11 9 180 0 9 180 0.25 24 144 0.32
protein-1 13X13 34 24 462 0.26 10 349 0.01 10 353 0.88 34 348 0.90
protein-2 13X13 51 25 662 0.28 31 566 0.02 31 566 0.92 51 607 0.91
dilution 15X15 54 15 1178 0.17 23 844 0.11 23 820 1.53 54 582 1.40
multiplex 15X15 59 36 1444 0.36 10 527 0.01 10 534 1.76 59 851 1.24
random-1 10X10 20 8 278 0.04 9 183 0.00 9 185 0.54 20 161 0.46
random-2 15X15 30 11 614 0.10 16 421 0.02 16 421 1.63 30 476 1.32
random-3 20X20 60 19 2720 0.31 27 1099 0.25 27 1090 3.53 60 808 3
random-4 30X30 90 26 5975 0.40 46 2127 0.74 45 4076 29.10 90 1826 10
random-5 50X50 100 37 7965 1.53 28 3994 2.22 28 3830 65.82 100 3814 42.70 random-6 60X60 100 41 8901 2.23 39 3247 1.65 35 2695 118.65 100 3223 54.10 random-7 70X70 150 80 16612 6.65 52 5063 6.9 45 7133 232.40 150 6188 59.86
Norm. - - 1.11 2.51 1.05 1.00 1.00 1.00 0.96 1.17 38.3 2.58 1.02 31
Table 5.2: Comparison with Prior Work [3] on Obstacle Aware Pin-Constrained Designs
[3] Our Work(ILP-Based)
benchmarks Size #E Pmax #Pin #WL CPU Time(s) #Pin #WL CPU Time(s)
DNA-1 16X24 211 128 128 3003 3.7 128 2335 7.3
DNA-2 13X21 77 32 32 1113 0.7 32 894 2
random-1 6X8 24 16 16 271 0.0 16 206 0.28
random-2 15X15 59 32 32 991 0.4 32 893 1.47
random-3 15X15 62 32 32 1153 0.5 32 872 1.45
random-4 15X15 91 64 64 1417 0.4 64 1244 1.6
random-5 20X30 256 128 128 4742 11.4 128 3969 16.9
random-6 30X40 400 256 256 9099 26.1 256 6959 72.2
Norm. - - - 1.00 1.25 - 1.00 1.00
-In this section, experimental result of the proposed algorithm is presented. The entire algorithm is implemented with standard C++ language and experimented on
(a) Merging Effort vs Reduction in activation sequences
(b) Reduction in activation sequences vs Routed wirelength
Figure 5.1: Tradeoff between reduction number in activation sequences, routed wire-length and merging effort for obstacle free testcase [random-3].
AMD Athlon Dual Core machine operating at 2.6GHz. IBM CPLEX v12.2 [1] is used to solve the ILP constraints in escape routing. Input designs are obtained from [8] and input designs with obstacles are obtained from [3]. Execution time for [8]
and [3] is presented based on their reported statistics.
To demonstrate effectiveness of routability driven clustering, we compare our algorithm with [8]. Fig. 5.3 illustrates the routing result using our algorithm and [8]. Unlike [8], our algorithm does not require to find minimal spanning tracks as an initial solution. Our proposed clustering algorithm simply finds a proper merging order to maximize routability. In Table 5.1, #E denotes total number of electrical pins. #Pin denotes total number of required activation sequences and #WL de-notes total routed wirelength. In comparison with [8], our proposed algorithm at default mode achieves 11% additional reduction in required activation sequences and routes the designs with an average of 151% less total wirelength using equivalent execution time. The reduction in routed wirelength have direct impact to reduction
(a) Merging Effort vs Reduction in activation se-quences
(b) Reduction in activation sequences vs Routed wirelength
Figure 5.2: Tradeoff between reduction number in activation sequences, routed wire-length and merging effort for obstacle free testcase [dilution].
point, when routed wirelength begins to detour to search for a feasible solution, improvement in reduction of activation sequences terminates almost instantly.
When execution time and routed wirelength are not the primary concerns, using ILP based escape routing algorithm to route all of the paths, we can achieve 15.6%
reduction in activation sequences and 113.8% less total wirelength using 38x more execution time compared to default mode. In comparison with direct-addressing method, our proposed framework can reduce activation sequences by 158% with 2%
less wirelength. To maximize routing success rate, ILP based escape routing is used to route all of the paths in direct-addressing method.
Our algorithm is also capable of dealing with designs with presence of obstacles.
Table 5.2 lists the designs with presence of obstacles and compares our result with work done in [3]. Our framework can still achieve equivalent number of reduction in activation sequences with 25% improvement in total routed wirelength.
The entire framework has two input parameters, α, to control greediness of clustering and β, to control degree of detour when congested region is encountered.
When α is set to 0, merging effort is set to zero and our framework behaves exactly like direct addressing method. When α is set to 1, merging effort is to the maximum and our framework will greedily reduce total number of activation sequences.
(a)
(b)
Figure 5.3: Merging and routing result for testcase [Amino-Acid-1] Compared with work [8] for test case [amino-acid-1]. (a) Our work requires 7 activation sequences using 185 unit of routed wirelength. (b) [8] requires 9 activation sequences using 190 unit of routed wirelength.
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160
Figure 5.4: Routing result for testcase [random-6] with presence of obstacles.
Chapter 6 Conclusion
In this work, we solved both merging and routing problem for pin constrained Broadcast Addressing EWOD chips. Our main contribution lies in our proposed routability driven clustering to determine merging priority of electrical pins. Us-ing diagonal of overlappUs-ing boundUs-ing boxes can accurately estimate routability and achieves better reduction in activation sequences. The nature of clustering frame-work offers flexibility to de-cluster when routing failed and obtains a precise tradeoff between reduction in activation sequences and routed wirelength. The multi-source multi-sink routing problem can be formulated as a set of ILP constraints and op-timally solved. As a result, our proposed algorithm outperforms recent works on pin-constrained EWOD designs with and without presence of obstacles with at most 15% reduction in activation sequences.
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