VRN VRP
VSS
Ion Iop
M5 M6
M1 M3 M4 M2
Figure 4.6: Schematic diagram of preamplifier 1.
Vip
VB1 VRN
VSS
Ion Iop
Vin VRP
M5 M6
M1 M3 M4 M2
Figure 4.7: Schematic diagram of preamplifier 2.
4.3. ANALOG CIRCUITS 85
Figure 4.8: Schematic diagram of comparator.
prevent the common mode difference between input signal and reference voltage from translating into differential signal, the common-mode voltage of input signal should be set to VRP+V2 RN.
The overall comparator topology is shown in Fig. 4.8. The comparator consists of a differential-difference preamplifier with a voltage gain of 9, followed by a regenerative latch. The active loads formed by transistors M7,M8,M9 and M10 acts as a current-to-voltage converter with a high output impedance. The dynamic comparator uses a set of two NNOS transistors, M11 and M12, operating in the active region and connected to the preamplifier. These transistors can be regarded as a voltage-to-current translator which generates the current difference. As the upper cross-coupled latch (M13,M14,M17 and M18) has positive regeneration when the control signal φ goes high, the drain currents of the active switching NMOS are steered to reach the final state determined by the current difference.
In Fig. 3.13, the threshold voltages for the two comparators are ±0.25Vr. In this design, the differential Vr is 1.4 V, and its common-mode voltage is 1.35 V. Thus, the corresponding reference voltages for VRP and VRN in Fig. 4.8 are 1.525 V and 1.175 V
Table 4.2: Transistor dimensions of the comparator.
Transistor Width(µm)/Length(µm)
M1, M2, M3, M4 16/0.5
M5, M6 20/1.2
M7, M8 3/0.35
M9, M10 2.8/0.35
M11, M12 8/0.25
M13, M14 8/0.25
M15, M16 2/0.35
M17, M18 12/0.25
respectively. The transistor dimensions of the comparator are listed in Table 4.2.
4.4 Digital Circuits
Digital functional blocks, such as calibration processor and output encoder, are also inte-grated in the same chip. Due to the immense complexity of this system, the background calibration algorithm was first verified with behavioral C before functional mixed VER-ILOG/VHDL simulations are performed. For this purpose, VHDL models were devel-oped for all analog blocks including offset and mismatches related errors. For the digital block, the algorithm first was translated into RTL codes in VHDL, which RTL was then combined with the analog VHDL models to verify the functionality of the design. Fi-nally, RTL was synthesized to generate the structural VERILOG descriptions based on the standard cell models. The layout based on the synthesized VERILOG descriptions was automatically placed and routed by commercial CAD software.
Fig. 4.9 shows the block diagram of the Rji extractor. The low pass filter (LPF) in Fig. 3.16 is realized with a simple accumulator. The digital output from the z-ADC, Dz, is first correlated with the random sequence q0 before being integrated by the accumulator.
The resulting output Dyis taken only after M cycles of integration, where M is the period of the random sequence q.
Referring to Fig. 4.9, the analog signal can be assumed to be embedded in Vj+1 for nominal A/D conversion is uniformly distributed between +0.5Vr and −0.5Vr and the
4.4. DIGITAL CIRCUITS 87
Figure 4.9: Block diagram of Rjiextractor.
quantization step size for a Z-bit z-ADC is Vr/2Z. This Vj+1 causes a fluctuation in Dy, resulting in a varying Rji. The variance of Rjcan be expressed as [18]:
σ2 Rj
where N is the number of Csfragments as defined in (3.36). By letting σ Rj be smaller than one half of the z-ADC’s quantization step size, the following is obtained:
M ≥ N
3 ×22Z (4.27)
Thus, the required calibration time for the j-th stage is 2N × M = (2/3)N2 ·22Z. Obviously, large M is required for high resolution, but it also leads to slow calibration process. (4.27) demonstrates that in order to attain 15-bit ADC using the pipeline stage shown in Fig. 3.13 with N = 4, one can choose M1 = 228for the 1st stage, M2 = 226for the 2nd stage, M3 = 224for the 3rd stage, and Mn = 230−2nwhere n is the stage number.
However, simulation reveals that the resulting ADC does not reach 15-bit resolution due to the accumulation of Rj errors from the cascaded stages. A better choice is to have M1= 228, M2 = 227, M3 = 226, and Mn = 229−nwhere n is the stage number.
To simplify the design of this ADC prototype, M = 228 is chosen for all calibrated stages. For this ADC prototype, only the first five pipeline stages are calibrated. For one calibration cycle, the calibration proceeds backward and sequentially, i.e., from the 5th stage toward the 1st stage. When calibrating the 5th stage, the z-ADC is the pipeline from the 6th stage to the 18th stage. When calibrating the 4th stage, the z-ADC is the pipeline from the calibrated 5th stage to the 18th stage. When the j-th stage is under calibration,
the Rji(Dc) values are measured sequentially for i = 1, 2, 3, 4 and Dc = −1, +1. A total of eight Rji values have to be measured for each calibrated stage. These values are used to compute Rj(−1) and Rj(+1). The value for Rj(0) is preset to 0. A total of 40 × 228sampling periods are required to complete one calibration cycle, which translates to 4.5 minutes for a sampling rate of 40 MS/s. During the initial power-up, the full-cycle calibration time is reduced to 0.065 second by shorting the SHA’s inputs to zero and setting M = 216. By shorting the inputs, the σ2 Vj+1 term in (4.26) becomes zero, and M can be reduced to speed up the calibration process.
The total logic gate count of the chip is approximately 27,000. The largest adder is the 48-bit accumulator used in the Rjiextractor. This ADC prototype does not require a multi-bit multiplier.
4.5 Experimental Results
Fig. 4.10 shows the chip micrograph of the fabricated ADC. The process is 0.25 µm 1P5M CMOS technology and has standard threshold voltage levels of 0.53 V and -0.53 V for NMOS and PMOS devices respectively. The chip dimensions are 3.8 × 3.6 mm2. The die was packaged in a 64-pin TQFP package. Digital circuits occupy 12% of the total area. In mixed-signal chips, some strategies are required to minimize the impact of noise coupling from the digital circuitry to the sensitive analog circuitry via the common substrate. In this layout, the following approach was taken. The digital and analog blocks use separate power lines. Because an n-well process was used, the digital and analog PMOS transistors were naturally isolated by separate wells. The NMOS transistors, however, interact with each other via the common substrate. Because the substrate material is made of lightly doped p- material, traditional isolation using deep n-well guard rings to collect noise is effective enough. Thus, the analog block is surrounded by analog VDD and VSS power lines. Decoupling capacitors formed by PMOS and NMOS devices are buried underneath the analog power lines. This guard-ring structure shields noise coupled from the digital block via the substrate.
For the analog NMOS transistors, it is important that the source-to-body voltage is constant. Otherwise, if these voltages move relative to each other, the drain current is
4.5. EXPERIMENTAL RESULTS 89
Figure 4.10: ADC chip micrograph.
modulated through the body effect. Therefore, it is important to locally have a low-resistance path from body to source. In the layout, a p+ substrate ring was placed around each NMOS analog transistor. This ring was then contacted to analog VSS power lines, which is at the same potential as the source for common-source devices. This helps keep the source and the body at the same potential.
Operating at a 40 MS/s sampling rate under a single 2.5 V supply, the analog block consumes a total of 350 mW of power while the digital block consumes only 20 mW.
In order to evaluate the 15-bit ADC properly,the test system was carefully configured to minimize various effects, such as input signal distortion,test-board noise,and clock jit-ter, which would destroy the measurements. A four-layer printed circuit board was used to provide good power and ground planes and to shield all critical signal paths. The sinewave generator is the Agilent 14438c with 16-bit DAC output. The sinewave input signal is fil-tered with a 4-tap passive LC bandpass filter to further reduce any remaining harmonic distortion. Before going into the ADC, the single-ended sinusoidal source drives an exter-nal center-tapped transformer which then applies the resulting differential signal directly to the inputs of the converter. The output data from the ADC were collected by logic analyzer, the Agilent 16702B equipped with 32MB memory. The logic analyzer operated in sampling mode. The sampling clock also came from the ADC.
Fig. 4.11 and Fig. 4.12 show the ADC’s differential nonlinearity (DNL) and integral nonlinearity (INL) characteristics obtained from code-density measurements. Notably, the LSB is normalized to 16-bit resolution in those figures. The number of registered output codes is approximately 3/4 × 216. Fig. 4.11 shows the ADC’s native DNL and INL before activating the calibration processor. The DNL is+1.2/ − 0.6 LSB and the INL is+15/ − 15 LSB. Fig. 4.12 shows the ADC’s DNL and INL after the background calibration is activated. The DNL is reduced to+0.34/−0.25 LSB and the INL is reduced to+3.4/ − 4.0 LSB.
Fig. 4.13 shows the ADC’s output FFT spectra at a 40 MS/s sampling rate. The input is a differential 2.0 Vpp 8.30 MHz sinusoidal signal. Without calibration, the 3rd-order harmonic is the dominant distortion term, which is −76 dB below the fundamental signal.
The signal-to-noise-plus-distortion ratio (SNDR) is 68 dB and the spurious-free dynamic range (SFDR) is 76 dB. After the background calibration is activated, the SNDR is
im-4.5. EXPERIMENTAL RESULTS 91
Figure 4.11: Measured DNL and INL at 40MS/s with calibration off.
Figure 4.12: Measured DNL and INL at 40MS/s with calibration on.
Figure 4.13: Measured output FFT spectra. The 2.0 Vpp8.30 MHz differential sinusoidal input is sampled at 40 MS/s.
proved by 5.5 dB to 73.5 dB and the SFDR is improved by 17.3 dB to 93.3 dB. Notably, the ADC’s signal-to–noise ratio (SNR) remains almost the same before and after cali-bration. The SNDR/SFDR improvement after calibration comes from the elimination of harmonic tones.
Fig. 4.14 shows the ADC’s measured SNDR and SFDR versus input frequencies at a 40 MS/s sampling rate. The SNDR and SFDR change little up to the Nyquist frequency.
Generally, the calibration can improve the SNDR by 5.5 db and the SFDR by 17 db.
Fig. 4.15 shows the ADC’s SNDR versus input signal level with calibration on and off respectively. The 1 MHz sinusoidal input is sampled at 40 MS/s. The data reveal that the total noise power, excluding distortions, is not affected by the input level. The noise power does not increase when the calibration is on. Thus, the random term Rji injected into the analog signal path is fully removed in the digital output. The measured dynamic range is approximately 78.5 dB.
Table 4.3 summarizes the measured performance of the ADC prototype at room tem-perature.
4.5. EXPERIMENTAL RESULTS 93
Figure 4.14: Measured SNDR and SFDR versus input frequency at 40 MS/s sampling rate.
Figure 4.15: Measured SNDR and SNR versus input level. The 1 MHz differential sinu-soidal input is sampled at 40 MS/s.
Table 4.3: ADC performance summary
Technology 0.25 µm CMOS
Chip Area 3.8 × 3.6 mm2
Supply, VAA/VDD 2.5/2.5 V
Power, PAA/PDD 350/20 mW
Max. Sampling Rate 40 MS/s
Differential Input Range 2.1 Vpp
Number of Output Codes (3/4) × 216 DNL, normalized to 16 bits −0.25/+ 0.34 LSB INL, normalized to 16 bits −4.00/+ 3.40 LSB SFDR, fs = 40 MS/s, fin=8.03MHz 93.3 dB SNDR. fs = 40 MS/s, fin=8.03MHz 73.5 dB
4.6 Summary
To verify the proposed background calibration technique, an experimental prototype was designed and fabricated. Besides the analog circuits, the digital blocks which contain the background calibration algorithms are also integrated into the same chip. The system consists of an input Sample-and-Hold followed by 17 radix-2 1.5-b SC pipelined stages and a final 2-b flash stage. Only the first five pipeline stages were designed to employ the proposed background calibration scheme.
The ADC was fabricated using a 0.25 µm 1P5M CMOS technology. The process has standard threshold voltage levels of 0.53 V and -0.53 V for NMOS and PMOS devices respectively. The maximum rated voltage supply is 2.5 V. Linear capacitors were im-plemented using metal-insulator-metal (MIM). The capacitance of these capacitors was approximately 1 fF/µm2. The die was packaged in a 64-pin TQFP package. Operating at a 40 MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio (SNDR) of 73.5 dB and a maximum spurious-free-dynamic-range (SFDR) of 93.3 dB.
The chip occupies an area of 3.8 × 3.6 mm2, and the power consumption is 370 mW with a single 2.5 V supply.