With the increasing number density, and correspondingly small feature sizes, of dynamic random access memory (DRAM) devices, it is becoming increasingly difficult to obtain sufficient cell capacitance to satisfy device refresh requirements[21,84]Many of the materials
initially investigated as prospective alternative dielectric layer candi-dates were inspired by memory capacitor applications and the resul-tant semiconductor manufacturing tool development infrastructure.
The most commonly studied high-k gate dielectric candidates are Ta2O5, SrTiO3, HfO2, ZrO2, and Al2O3, which have dielectric constants ranging from 10 to 80, and have been employed mainly due to their maturity in memory capacitor applications[85]. Thin dielectric amor-phousfilms of ZrO2and HfO2have been intensively investigated as replacements for SiO2as the gate dielectric oxide in sub-45 nm CMOS technology [85]. This is due to their relatively high permittivities (k ~ 14–25; for amorphous phase) compared with SiO2(k ~ 3.9), large band offsets, large bandgaps and high thermodynamic stability on sili-con. ZrO2and HfO2also have promising applications as capacitor layers in metal–insulator–semiconductor (MIS) and metal–insulator–metal (MIM) DRAM devices[61,79,80].
4.1. Dielectric properties of ZrO2film on Si(001)
Dielectric properties and conduction mechanisms of ultrathin RTCVD grown bilayer ZrO2films (top 1.9 nm amorphous and bottom 2.5 nm polycrystalline) have been reported by Chang and Lin[60].
Fig. 4(a) shows C–V characteristics of as-deposited 7.5-nm-thick a-ZrO2 MOS capacitors on p-Si(001) [Al/ZrO2/p-Si(001)] with a small hysteresis (b50 mV). The calculated average dielectric constant is ~ 16, and it varies between 15 and 18 depending upon the process-ing conditions. A plot of EOT versus physical thickness of the a-ZrO2 films yields an intercept at essentially zero EOT (0.08 nm) indicating no interfacial SiO2formation, as shown inFig. 4(b). However, due to mixing, interfacial ZrSixOyis formed, as shown in the high resolution transmission electron microscopic (HRTEM) image inFig. 4(c). Taking into account the interfacial ZrSixOylayer and the physical thicknesses (7.5-nm-thick a-ZrO2) of the dielectric layers, the dielectric constant of ZrSixOyis 11 and the dielectric constant of ZrO2is 21. The calcu-latedflatband voltage is −0.7 eV.
n-MOS transistors using 15-nm-thick a-ZrO2 and n+-polysilicon gate electrode were also fabricated and good device turn-on character-istics are shown inFig. 5. The reduced transconductance (gm), of the order of 10−4S, is most likely due to the high source and drain contact resistances (Rsand Rd) resulting from incomplete removal of the inter-facial ZrSixOy layer with an HF etching process. An approximately 0.3-nm-thick interfacial zirconium silicate layer is responsible for the reduced mobility. This clearly indicates the necessity of more effective ZrO2and ZrSiO4patterning to minimize the device integration dif ficul-ties[60]. A sputter deposited ZrO2-based MIS structure on n-Si(001) with an Al top electrode, having an equivalent-oxide thickness (EOT) of ~2.5 nm, has been also reported[86]. Optimized devices showed less than 2 × 10−5A/cm2leakage current density at 1 V accumulation bias, which is lower than SiO2-based gate dielectric devices with similar EOT. Formation of a 1.7-nm-thick zirconium silicate interfacial layer was confirmed by HRTEM analysis. The interfacial silicate layer was found to play a crucial role in determining the conduction mechanism in the high-k MIS structure[86].
Koo et al.[66]measured the leakage current characteristics of a Pt/p-ZrO2/p-Si(001) MOS capacitor under negative bias as shown inFig. 6(a). At−1.0 V gate voltage, the leakage currents of ALD-grown p-ZrO2 films, using ZTB as a zirconium precursor, depos-ited in oxygen gas (film thickness: 6 nm) and in an oxygen plas-ma (film thickness: 6.5 nm) were approximately 3.7×10−7 and 2.7 × 10−8A/cm2, respectively. Sequential times of Zr-precursor, Ar-purge, O2gas, and Ar-purge werefixed to be 5 s each except for the O2 plasma process time which was 10 s. 100 Watt rf power, 250 °C substrate temperature, and 1 Torr process pressure were used[66]. The corresponding extracted EOT at 1 MHz accumulation capacitance were about 2.85 and 3.31 nm for ZrO2films deposited with the oxygen gas phase and oxygen plasma ALD, respectively.
The low leakage current compared to that of conventional SiO2gate
dielectrics with the same EOT was attributed to the enhanced physical thickness of polycrystalline ZrO2 (p-ZrO2) with a higher dielectric constant (~25) and a larger bandgap (7.8 eV). The effective dielectric constants were calculated to be 10.94 for ZrO2grown from oxygen ALD and 11.2 for plasma ALD. The low effective dielectric constant, com-pared to the bulk dielectric constant (25) is due to the effect of the 2–3 nm interfacial Zr-silicate (ZrSixOy) layer. Interface state densities were calculated to be 1.16× 1011and 5.52 × 1012eV−1cm−2from the high frequency C–V curves,Fig. 6(b). Due to plasma-induced defects in thefilm and/or at the interface, the interface density was higher for the plasma ALD layer.
Qi et al.[52]obtained less than 1.1 nm equivalent oxide thick-ness with 1.93 × 10−3A/cm2 leakage current density at −1.5 V for a Pt/a-ZrO2/p-Si(001) MOS capacitor. The deposition details are de-scribed inSection 2.1. Less than 1011cm−2eV−1interface state density was calculated from the high frequency C–VGcurve shown inFig. 7(a).
No frequency dispersion was observed between 100 kHz and 1 MHz.
However, the hump in the C–V curves at ~0 V is due to slow traps. No trap generation was observed during a stress-induced leakage current study. A stress-related 120 mV shift in gate voltage (ΔVG) has been reported for a 2-nm-thick ALCVD-grown p-ZrO2film on p-epi/p+ sili-con with an Al/TiN top electrode after 10 successive ±2 V sweeps by Perkins et al. [11]. The process details have been described in Section 2.3. Gate stacks with EOT = 1.3 nm showed leakage values of 10−5A/cm2 at a bias of−1 V, which is significantly less than that seen with SiO2dielectrics at similar EOT[11]. MOS capacitors of RTCVD grown a-ZrO2on p-Si(001), using a ZTB metalorganic pre-cursor[59], showed good inversion with a small but noticeable C–VG
hysteresis (50–100 mV), as shown in Fig. 7(b). The dielectric constant varied from 15 to 18 depending on the deposition condi-tions. A low leakage current density of 10−3A/cm2at−1.5 V for EOT = 2 nm has been reported. This is a few orders of magnitude lower than that of thermally grown SiO2with comparable oxide thickness, as shown inFig. 7(c)[59].
C (µF/cm2)
V (Volts)
102
100 10-2
10-4 10-6
10-8
10-10
Tox (Å) I (A/cm2) @ -1.5V
a
c
b
35 30 25 20 15 10
Fig. 4. (a) C–V characteristics of an Al/7.5-nm-ZrO2/Si capacitor. (b) The leakage current I vs. oxide thickness toxmeasured at−1.5 V. The solid line represents the leakage current (I) measured for thermally grown SiO2at the same equivalent oxide thickness[60]. (c) HRXTEM image of a ZrO2/ZrSixOyfilm stack on crystalline p-type Si(001). The upper selected area electron diffraction pattern is from the ZrO2/ZrSixOybilayer, while the lower one is from the Si(001) substrate. The lower part of the ZrO2layer is monoclinic polycrystalline while the upper part is amorphous[60].
VG (V)
b
4×10-5
3×10-5
2×10-5
1×10-5
0
0 1 2 3 VD (V) ID (A)
a
4 5
Fig. 5. (a) Drain current (ID) vs. drain voltage (VD) for a n+-poly/15-nm-thick-ZrO2/p-Si(001) transistor. (b) IDvs. gate voltage (VG) curve of the same device[60].
Ramanathan and McIntyre[87]reported severe distortion of C–V curves in both depletion and accumulation regions due to defects in a ultra high vacuum (UHV) sputter deposited p-ZrO2 based MOS capacitor on an HF treated p-Si(001) substrate (details of the growth
process described inSection 2.1 [49]). A detailed study of the inter-face reactions between sputtered polycrystalline Zrfilm and Si(001) has been performed by Sun et al.[88]. Generally there is a tendency to form silicate or silicate oxides at the Zr/Si or ZrO2/Si interface.
This can significantly affect the electrical properties of the dielectric layer. The distorted C–V curves noted above were attributed to under-oxidized dielectric layers and interfacial-polarization phenom-ena[87–89]. Only a small frequency dispersion in accumulation has been reported in 2-nm-thick ZrO2film grown on ultrathin (1.1 nm) SiO2, due to the effects of series resistance arising from a resistive substrate[87,90].
A 1.5 nm equivalent oxide thickness was estimated from the C–V curve. A high dielectric constant (k) of 18–19 with low leakage current density were obtained in MOMBE grown ZrO2on p-Si with an Ag top electrode[74]. Dielectric properties of a 4-nm-thick ALD-grown ZrO2 layer on native oxide (1.2 nm) coated Si(001) have also been reported [91]. After PDA at 700 °C for 5 min in O2at atmospheric pressure, multiphase (~with over 90% by volume predominantly tetragonal-ZrO2(t-ZrO2) and monoclinic-ZrO2(m-ZrO2) nanocrystals) and het-erogeneous structure evolved. The effective dielectric constant of a Pt/ZrO2/SiO2/Si(001) MOS capacitor was significantly reduced due to its nanochemistry, although the effective k of the interfacial layer was increased[91].
Of the several advantages of ZrO2in gate dielectric applications, such as wide bandgap, suitable dielectric constant, low interface trap density, process compatibility etc., one issue is C–V hysteresis [92–96]. This hysteresis induces aflatband voltage shift, leading to threshold voltage instability, when ZrO2is used as a gate dielectric.
Such hysteresis phenomenon may be due to chemical contamination from ALD precursors, stress-induced defect formation, or mobile ions [96,97]. Wang et al. was studied this phenomenon and explained it using an inner-interface trapping model for ultrathin (EOT ~ 1.5 nm) ALD grown 5-nm-thick ZrO2films using ZrCl4and H2O precursors at 300 °C and 1 Torr pressure[96]. A serious charge trapping phenome-non (flatband voltage shift: ~45 mV) has been reported due to the in-fluence of light on charge trapping at the ZrO2/Zr-silicate interface.
It was proposed that UV irradiation can improve electrical prop-erties leading to a low leakage current density of 8.3 × 10−8A/cm2 at 1 MV/cm and a breakdown field larger than 4 MV/cm [76]
for chemically grown metastable ZrO2 (t-ZrO2 and m-ZrO2) films on p-Si(001) with an Al gate (growth process is described in Section 2.5). UV (172 nm) irradiation at ~ 300 °C in 0.75 Torr oxygen pressure for 5 min dramatically reduced the density of positive fixed-oxide charges near the ZrO2/Si interface, resulting in a low pos-itive charge density of 3.2 × 1010cm−2. Harasek et al.[98]reported a PDA effect (650 °C to 800 °C for 5 min in forming gas and diluted O2) on the electrical properties of MOCVD grown ZrO2MOS capacitor on p-Si(001) at 450 °C, using Zr(tfacac)4 precursor, with an Al top electrode and an EOT of 2 nm. Interface trap densities (DIT) of
b
3.5E-10 3E-10 2.5E-10 2E-10 1.5E-10 1E-10 5E-11
Capacitance (F)
1
a
0.01
1E-4
1E-6
1E-8 J (A/cm2)
VG(V) VG (V)
O2 gas phase O2 plasma
state
O2 gas phase
O2plasma state
-16 -14 -12 -10 -8 -6 -4 -2 0 -3 -2 -1 0 1 2 3
Fig. 6. (a) Leakage current density (J) vs. gate voltage (VG), and (b) high-frequency capacitance (C) vs. VGcharacteristics of a Pt/ZrO2/p-Si(001) capacitor in which the ZrO2layer is deposited in oxygen gas and oxygen plasma[66].
EOT=1.06 nm
EOT=1.38 nm
Tox (Å) I (A/cm2) @ -1.5V
5×10-10
b
4×10-10
3×10-10
2×10-10
1×10-10
0
C (F)
V (V) c
-4 -2 0 2
a
Fig. 7. (a) High frequency C–V characteristics of Pt/ZrO2/Si structures[50]. (b) C–V responses, and (c) the leakage current I vs. oxide thickness toxmeasured at−1.5 V of planar 7.5-nm-thick ZrO2based MOS capacitors on Si with Al top electrode[59].
approximately 53× 1011cm−2eV−1and a small oxide charge density in combination with a leakage current density of 43× 10−6A/cm2 have been reported for ZrO2films having an EOT of 3 nm. An oxidizing atmosphere during the annealing process leads to inferior electrical characteristics with regard to interface trap density, oxide charge, and insulator leakage due to the formation of an increased trap density[98].
4.2. ZrO2-based MIS structures on strained Si and SiGeC
Strained-Si based MOSFETs are promising candidates for next gener-ation complementary MOS technology[99–101]. In tensile-strained Si layers grown on relaxed-SiGe substrates, mobility enhancements over bulk Si of roughly 60% for holes and 80% for electrons were achievable [99–104]. This corresponds to a considerable performance enhancement over current Si MOS devices; however, strained-Si technology must be compatible with the standard CMOS process. Maiti et al.[99,100] stud-ied the quality of thin low-temperature (150 °C) microwave plasma (700 W, 2.45 GHz) CVD grown high-k ZrO2films on tensile-strained p-Si(001) on relaxed Si0.91Ge0.09layers at a pressure of 500 mTorr and reported a very low leakage current density of 10−7A/cm2at−1 V.
The calculated interface state density was comparable with those reported for ZrO2films deposited directly on Si(001) using other tech-niques. The conduction mechanism was found to be dominated by Schottky emission. Bandgap and strain engineered Si1−x−yGexCyalloys are also attractive for high performance silicon heterostructure devices [101–107]. Chatterjee et al.[101]deposited SiO2/ZrO2film stacks on strained-Si0.91Ge0.09/Si(001) layers at low temperature (150 °C, 30 s) by microwave plasma (700 W, 500 mTorr) deposition. An effective di-electric constant of ~13.3 was calculated from the analysis of high fre-quency C–V characteristics of the stacked-gate MIS capacitors. By calculating interface trap charge density from the C–V characteristics of as-deposited and 500 °C annealed in pure nitrogen ambient for 30 min samples, ZrO2and stacked SiO2/ZrO2samples indicate that the interface quality was improved by introducing an ultrathin SiO2layer.
However, further improvement was also observed after annealing the samples at 500 °C for 30 min. Mahapatra et al.[103]investigated the interfacial structure and electrical properties of sputtered ZrO2films, using a ZrO2target, on strain-compensated Si0.69Ge0.3C0.01/Si(001) layers with an Al top electrode. A 350 °C substrate temperature, 50 Watt rf power, and a process pressure of 0.2 Torr have been used during 20 minute sputtering. Formation of an ultrathin Zr–Ge-silicate interfacial layer was realized from an HRTEM study. The ZrO2layers consist of a top p-ZrO2film with a thickness of ~8.5 nm and an a-ZrO2interfacial layer with a thickness of ~3.6 nm. A low leakage current of ~9×10−8A/cm2 at−1.0 V gate voltage, a high breakdown field of 7 MV/cm, and a mod-erate interface state density of 6×1011cm−2eV−1were observed in the stacked dielectricfilms with an EOT of ~1.9 nm for this mixed ZrO2
with a 2 nm interfacial silicate layer. High dielectric constants of ~17.5 for ZrO2and ~7.0 for the interfacial silicate layer were calculated from the C–V analysis.
4.3. ZrO2-based MIS structure on III–V semiconductors
The understanding of III–V MOSFETs requires gate dielectrics that allow for low gate leakage currents and a low density of interface states.
A primary challenge in the growth of high-quality III–V/dielectric inter-faces is that even sub-monolayer coverages of oxygen pin the Fermi level of the III–V semiconductor [108,109]. Moreover, native III–V oxides cause interface instability, which must be minimized before and during dielectric deposition[108,109]. Engel-Herbert et al.[109]
reported the properties of CBD grown ZrO2MOS capacitors, using a zir-conium tert-butoxide [Zr(OC(CH3)3)4] metalorganic precursor at 225 and 470 °C (15 to 60 min) without using any carrier gas or additional oxidant, on in situ arsenic (As) capped In0.53Ga0.47As(001) substrate.
Pt, Mo, or Ta metal gates are evaporated with areas from 7.8 × 10−5to 4.9 × 10−4cm2through a shadow mask for MOS capacitive structures.
Low frequency dispersion (b2%), an accumulation capacitance and hor-izontal position of the CV curve with temperature independent, shifted flatband voltages with metal gate work function, and surface potential responded with the applied gate voltage were observed in the opti-mized 30-nm-thick ZrO2based III–V MOSFETs with a Pt gate electrode.
Strongly temperature dependent inversion capacitance was also no-ticed[109].
4.4. MIM capacitor based on ZrO2
In terms of the bottom electrode, highly doped poly-Si is typically used in DRAM capacitors. However, it easily reacted with high-k di-electric materials and generated thick interfacial oxides having low dielectric constants[110,111]. Thus, MIM capacitors using different metals, such as Pt, Ru, Ta, and W as bottom electrodes, have been con-sidered for future capacitor structures[111,112]. MIM capacitors of ALD grown t-ZrO2 on W/TiN/SiO2/Si(001) with a Pt top electrode have been reported by Lee et al. [111]. 50-nm-thick W was also grown by ALD. 11–11.5 nm t-ZrO2 was deposited at 300 °C using ZrCl4and H2O precursors. Both the precursors were pulsed for 2 s and N2purging followed for 30 or 60 s after H2O or ZrCl4pulsing, respectively. A thin interfacial amorphous layer of thickness of 1.3 to 1.4 nm was detected between the t-ZrO2and W layers. EOT of 2–2.1 nm and the effective dielectric constant (22–25) of the di-electric capacitor, including the contribution of interfacial WOxlayer have been reported[111].
Dielectric constants of around 26 and 24 for PLD (KrF excimer laser, 248 nm wavelength) grown a-ZrO2films deposited in N2and O2 ambient, respectively, with Pt top and bottom electrode have been reported [113]. Laser repetition rate of 5 Hz, 30 ns pulse width, energy density of 1.8 J/cm2, 300 to 700 °C substrate tempera-tures, and 0.15 Torr process pressure were used during a-ZrO2film deposition. Thefilm deposited in N2ambient had better frequency stability, smaller dielectric loss, and a smoother surface than the film deposited in O2ambient. Lower EOT of 1.38 nm and leakage cur-rent density of 94.6 × 10−3A/cm2were observed for thefilms depos-ited in N2ambient. This indicated that the dielectric property of the a-ZrO2films was improved by nitrogen incorporation[113].
A high dielectric constant of ~ 40 was observed for ALD grown ZrO2on TiN at 250 °C growth temperature using Zr(NEtMe)4and O3
sources[21]. The crystalline structures of this ALD grown ZrO2films was either tetragonal or cubic. Kim et al.[114] also reported that the leakage current and capacitance were decreased with increasing ZrO2thickness grown by ALD with TiN top and bottom electrodes (TZT). Zr[N(CH3)C2H5]4and O3precursors were used during growth process of ZrO2film at 225 °C, 250 °C, and 275 °C. ZrO2films deposit-ed at 225 °C and 250 °C were amorphous, while thefilms deposited at 275 °C were partially crystalline and at 300 °C the films were completely crystalline. The as-deposited a-ZrO2layer became crystal-line during PDA (400 °C, 1 min in N2) and/or top electrode formation at > 400 °C temperature. Low leakage current density (b10−8A/cm2) with high dielectric constant (~43) were calculated for 8-nm-thick crystalline ZrO2film deposited at 275 °C[114].
The influence of electrode roughness on the leakage current in TiN/ZrO2/TiN capacitors having t-ZrO2thicknesses of 10 and 7 nm, corresponding to EOTs between 1.0 and 0.7 nm (assuming a permit-tivity of 40 for t-ZrO2), has been studied by Jegert et al.[115]using a microscopic transport model. Tunneling transport in the dielectric bandgap was treated which incorporating defect-assisted transport mechanisms. Small electrode roughness does not influence the leak-age current significantly; however, thickness fluctuations have an important impact on the dielectric properties. For thinnerfilms, the transport mechanism transformed from Poole–Frenkel (P–F) conduc-tion to trap-assisted tunneling. As a result, the sensitivity of the leak-age current on electrode roughness dramatically increased upon downscaling[115].
Jegert et al. [116] also studied leakage currents using kinetic Monte Carlo (kMC) simulation of TZT capacitors with a t-ZrO2 dielec-tric. The transport model of a typical TZT capacitor with a k value of 38 is shown in Fig. 8. Defect density was assumed to be ND= 3 × 1018cm−3. For a TZT capacitor having an oxide thickness of 9 nm, the leakage current was dominated by P–F emission of elec-trons from positively charged defects at a donor level depth ED= 1.15 eV with respect to the ZrO2conduction band, at less than 2.5 V.
Electrons are injected from the TiN cathode into the defects through multi-phonon assisted and elastic tunneling. In the next step, de-trapping occurred via P–F emission into the t-ZrO2 conduc-tion band, where the electrons rapidlyflowed to the anode[116].
Thermally-activated de-trapping of electrons was the transport limit-ing step in this multistep process. Durlimit-ing injection steps for kMC sim-ulations, a conduction band offset (EB) between TiN and t-ZrO2 of 1.74 eV was extracted. Therefore, the defect level laid well above the electrode Fermi level. For applied voltage > 2.5 V, at lower tem-peratures (T≤50 °C), an increase of the slope of current–voltage curves was observed together with a reduced temperature scaling.
Here, trap-assisted tunneling (TAT) was dominant. At high voltages when the shape of this barrier changes from trapezoidal to triangular (seeFig. 8), the de-trapping rate increases with the applied voltage, so that itfinally exceeds the rate for P–F emission[116]. The increased slope was explained by the stronger voltage dependence of the weak temperature dependence of TAT. The P–F emission rate is higher than that for TAT over the entire voltage range so that PF emission domi-nates the leakage current for T≥90 °C.
4.5. Stacked ZrO2–Al2O3-based MIM capacitors
As the minimum feature size of DRAM shrinks, high-k dielectric materials have been investigated tofind an alternative for Al2O3as a dielectric in MIM capacitors with TiN electrodes. EOT lower than 0.9 nm will be required to obtain 25 fF/cell with a 1.3μm high cylin-drical capacitor structure. It was discussed above that quite different phases of ZrO2 have different dielectric constants. However, the high dielectric constant phases of ZrO2are unstable[117]. ZrO2MIM capacitors with TiN electrodes cannot be easily used due to high leak-age current, particularly, in negative bias. To solve these issues in DRAM, a different capacitive structure was introduced. A dielectric
As the minimum feature size of DRAM shrinks, high-k dielectric materials have been investigated tofind an alternative for Al2O3as a dielectric in MIM capacitors with TiN electrodes. EOT lower than 0.9 nm will be required to obtain 25 fF/cell with a 1.3μm high cylin-drical capacitor structure. It was discussed above that quite different phases of ZrO2 have different dielectric constants. However, the high dielectric constant phases of ZrO2are unstable[117]. ZrO2MIM capacitors with TiN electrodes cannot be easily used due to high leak-age current, particularly, in negative bias. To solve these issues in DRAM, a different capacitive structure was introduced. A dielectric