FPGA Based Evaluation Platform

We design a verification platform based on ARM-based platform. Basically, our platform is constructed with the configuration in Figure 41. FPGA based test environment. Our ARM emulation board mainly includes two parts, core module and logic module. In the core module, there are ARM966 CPU, embedded SRAM (1 Mbytes), and external memory interface. On the other hand, the dedicated accelerators are implemented on the logic module which is a FPGA (Filed-programmable Gate Array). Moreover, ARM board employs the AHB bus interfaces to communicate the core module and logic module. Besides, our ARM integrator baseboard employs JTAG (Joint Task Action Group) interface to connect with an ARM MultiICE. The MultiICE connects to a host commuter to conduct the communication between computer and ARM board. In the FPGA environment, we run the codec of MPEG-4 encoder to verify our BBME design. The BBME is implemented on FPGA, and ARM CPU takes charge of the remaining parts of MPEG-4 encoder. The architecture of BBME has passed the verification.

Embedded

Architecture of ARM platform based MPEG-4 Encoder with BBME

Figure 41. FPGA based test environment

Chapter 6

Conclusion and Future Works

In this thesis, we presented a low power ME design for bi-directional search. The proposed ME design contains two main parts, IME and MD-SME. For low power application, a BBME architecture that can process the forward and backward search in parallel is presented. Such a design can save twice memory access of current frame and then share the operation engine to keep hardware as busy as possible. For P-frame search, this parallel search architecture divides the original search into two sub-groups of partial P-frame search to double the processing throughput. For the hardware design, we proposed three new features to improve the hardware efficiency including MBPPU, hardware efficient LV2 design and integration of 16×16 and 8×8 searches. Besides the optimization of IME, we integrate the MD module into SME to avoid two loops processing of MD and SME to save power. In MD, this work adopts a new line-based algorithm to reduce the longer latency in the original two-dimension and avoid hardware idling. In SME, we adopt an architecture that processes 3 search locations in parallel to reduce memory access and power consumption. To enable the parallel processing of IME and MD_SME, the system pipelining is designed to enhance the throughput and avoid hardware idling. This work completes one bi-directional MB search in 147 cycles with 131 kilo gate count and 51 kilo bits on-chip memory using TSMC 0.18μm technology. The power consumption for CIF 30fps is 11.8 mW.

In the further works, we focus on integrating BBSME with H.264/MPEG-4 AVC standard [20], which supports multiple reference frames. With some minor modifications, this work can be extended to ME with any combination of multiple forward or backward reference frames for throughput improvement

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簡 歷

戴世炘 : 民國七十年生於台灣省新竹市。民國九十三年畢業於國立清華大學電機工程學 系，之後進入國立交通大學電子工程所攻讀碩士學位。從事多媒體視訊壓縮以及數位電 路設計方面的研究。

Shih-Hsin Tai was born in HsinChu in 1981. He received the BS degree in Electronic Engineering, National Tsing Hua University (NTHU), HsinChu, Taiwan in 2004. His current research interests are video compression and digital circuit design.