Architecture Comparison

For the low complexity EM-type soft BCH decoders, the architectures of a hard BCH decoder and two proposed soft BCH decoders are compared in TABLE 3.3. The two proposed soft BCH decoders are designed with H-EMS and BP-EMS respectively while hard BCH decoder is designed with inversionless Berlekamp-Massey (iBM) algorithm [63]. As compared with

Table 3.3: Comparison Table for an (N, K, t) BCH Code Hard BCH Soft BCH ^* Soft BCH ^**

(iBM) (H-EMS) (BP-EMS)

Register 5t + 2 2t²+ 5t 8t

Multiplier 3t + 3 2t 1

Constant Multiplier 3t t + 1 2t + 1

Squarer 0 2t 0

Inversion Unit 0 0 1

Latency 2N + 2t N + 2^2t+ t − 1 N + 6t²− t

* In the special case : t = 1, the number of multipliers and squarers is 0.

If t is very small, like 1 or 2, we can check all combinations of γci over GF (2) at one cycle.

**Registers can be inserted into composite field inversion to reduce the critical path with the doubled latency in EMS step.

the soft BCH decoder with BP-EMS, only half syndromes are required for soft BCH decoder with H-EMS. In H-EMS, 2t multipliers and 2t squarers are used to construct the B^odd. Notice that, if the error correcting capabilities is equal to 1, the number of multipliers and squarers is 0 because only S1 will be computed. The first row registers in the H-EMS can be shared with registers of the error locator part in error locator evaluator so that totally 2t²− 2t registers are used in this part. In BP-EMS, only 1 multiplier and 1 inversion unit are employed to evaluate Γ. Both the soft decoders take n clock cycles for syndrome calculator and error locator evaluator simultaneously and H-EMS and BP-EMS take 2^2t+ t − 1 and 6t² − t clock cycles respectively.

TABLE 3.4 illustrates the number of each component at t = 1, 2, and 12. Notice that the synthesis results in CMOS 90nm technology shows that the complexity ratio over GF (2¹⁶) among 16-bit register, multiplier, constant multiplier, squarer and inversion unit is 1 : 10 : 3 : 1.5 : 25. With this normalized ratio, Fig. 3.17 shows the normalized complexity analysis among hard and soft decoders. In large finite field operations, a multiplier is much more complicated than a register. Due to fewer number of multipliers, the proposed soft BCH decoders with more registers have much lower hardware complexity as compared to the hard BCH decoder with iBM algorithm under different error correcting capabilities t. Because of non-linear increment of the number of registers, the complexity of soft BCH decoder with

Table 3.4: Comparison Table under Different Correct Ability

Hard BCH Soft BCH Soft BCH Hard BCH Soft BCH Soft BCH Hard BCH Soft BCH Soft BCH (iBM) (H-EMS) (BP-EMS) (iBM) (H-EMS) (BP-EMS) (iBM) (H-EMS) (BP-EMS)

t = 1 t = 1 t = 1 t = 2 t = 2 t = 2 t = 12 t = 12 t = 12

*According to the synthesis results in CMOS 90nm technology, the complexity ratio over GF (2¹⁶) among Register, Multiplier, Constant Multiplier, Squarer and Inversion Unit is 1 : 10 : 3 : 1.5 : 25 SOFT BCH with H−EMS SOFT BCH with BP−EMS

Figure 3.17: Normalized hardware complexity analysis of BCH decoders over GF (2¹⁶).

H-EMS is less than that of hard BCH decoder only if t is smaller than 8 as shown in Fig. 3.17.

H-EMS is more suitable to be applied in small t application, like BCH (762, 752, 1) decoder defined in DMB-T system. In addition, the soft BCH decoder with BP-EMS can always provide lower complexity than hard BCH decoder. In this paper, we applied BP-EMS in the proposed design according to the high error correcting capability requirement. The proposed soft decoders, searching error locations at error locator evaluator procedure, lead to a lot of latency saving. Consequentially, the proposed soft decoders provide both higher throughput and much lower hardware complexity.

For further improvement on latency, H-EMS could complete all the computations in one cycle with less hardware overhead for small t. In addition, BP-EMS could insert registers into composite field inversion for operation frequency improvement. Although the latency

Table 3.5: Comparison Table for an (N, K; t) BCH Code

(N, K; t) (N, K; t) (N, K; t) (N, K; t) (255, 239; 2) (255, 239; 2) (255, 239; 2) (255, 243; 2) Hard BCH Hard BCH Soft BCH Soft BCH-Like Hard BCH Hard BCH Soft BCH Soft BCH-Like

with iBM with SiBM with CEMS with M-CEMS with iBM with SiBM with CEMS with M-CEMS

Register 5t + 2 7t + 2 2t²+ 5t 2t²+ 5t 12 16 18 18

*In the special case: t = 2, the number of multiplier and squarer is 0.

**The normalized complexity is in terms of number of 8-bit 2-to-1 multiplexer. According to the synthesis results in CMOS 90 nm technology, the complexity ratio over GF (2⁸) among a 8-bit 2-to-1 multiplexer, a squarer, a constant multiplier, a 8-bit register, a multiplier, a LUT and a 51-TIMER is 1 : 1.5 : 1.5 : 2.5 : 12 : 27 : 30.

in EMS step will be doubled, it is only few percentage of overall decoding procedure for long block length BCH decoders, resulting in that throughputs of the soft BCH decoder can be nearly doubled.

For the high performance EM-type soft BCH decoders, the architectures of hard BCH de-coders and the proposed soft dede-coders are compared in TABLE 3.5. The proposed soft BCH and BCH-Like decoders are designed with the CEMS approach and the M-CEMS approach respectively whereas the hard BCH decoders are designed with inversionless Berlekamp-Massey (iBM) algorithm [63] and simplified iBM (SiBM) algorithm [64].

Both the soft BCH and BCH-Like decoders are designed with 2t multipliers, 2t squarers and 1 LUT. Nevertheless, an additional ρ-TIMER is applied in the M-CEMS. The registers in the first row of B^odd and B^′odd matrice in the CMES and the M-CMES are applied to store the error locator set B, which is also stored in the registers of the error locator evaluator. Therefore, these registers can be shared, resulting in totally 2t² − 2t registers used in the CEMS and the M-CEMS. Note that in the special case: t = 2, the M-CEMS can be constructed without any multiplier and squarer since there are only two syndrome values: S1 and Sρ. In addition, the syndrome calculator and the error locator evaluator take N clock cycles simultaneously in the decoding process and the CEMS and the M-CEMS take 2^2t+ t − 1 and 2^2t+ 2t clock cycles respectively.

In finite field operations, a multiplier is more complex than a register and a multiplexer.

Due to fewer multipliers, the proposed soft BCH decoder with more registers and multiplexers as well as an additional LUT has similar hardware complexity while compared to the hard BCH decoders with iBM and SiBM algorithms. The proposed soft BCH-Like decoder has a little more hardware complexity due to an extra TIMER, which contains 2 or more multipliers dependent on the coefficient ρ. According to the synthesis results in CMOS 90 nm technology, the complexity ratio over GF (2⁸) among each 8-bit 2-to-1 multiplexer, squarer, constant multiplier, 8-bit register, multiplier, LUT and 51-TIMER is 1 : 1.5 : 1.5 : 2.5 : 12 : 27 : 30. The normalized complexity of the soft BCH and BCH-Like decoders is around (5t² + 49t + 26.5) and (5t² + 51t + 56.5) 8-bit 2-to-1 multiplexers while that of the hard BCH decoder with iBM/SiBM algorithms is (54t + 42)/(72t + 5) 8-bit 2-to-1 multiplexers respectively. For the high code rate BCH and BCH-Like codes, the error correcting ability t is small, implying that the proposed soft decoders can provide similar hardware complexity as hard decoders even though the complexity of hard and soft decoders is linear and quadratic to t respectively. For example, the normalized complexity of the soft BCH (255, 239; 2) and BCH-Like (255, 243; 2) decoders is around 144.5 and 133.5 8-bit 2-to-1 multiplexers while that of the hard BCH (255, 239; 2) decoder with iBM/SiBM algorithms is 150/149 8-bit 2-to-1 multiplexers respectively.Moreover, the proposed soft decoders have only 53% latency compared to that from the tranditional hard BCH decoders by searching for error locations at error locator evaluator procedure.

Chapter 4