2.1 Architecture of CMOS voltage mode image sensor
2.1.1 Architecture of 3T voltage mode sensor
In general, 3T voltage mode sensor pixel is composed of a reset MOS (Mreset), a photodiode (sensor) and an active device (Ms) as shown in Fig. 2.1. The active device serves as a voltage buffer which enhances the driving capability of the photodiode output. The fixed pattern noise (FPN) induced by the threshold voltage (Vt) variation caused by active device Ms is found to be significant. In order to suppress the FPN, the threshold voltage must appear as the first order term in the output voltage equation which can be cancelled by the following correlated double sampling (CDS) operation.
The source follower operation equation is shown as equation (2-1) and (2-2)
out pd GS follower output. The threshold voltage term can be cancelled by sampling twice (Signal and Reset) and then subtraction, that is, correlated double sampling (CDS).
However, the Vt may encounter body effect due to the difference source voltage of the source follower. It would reduce the performance of the CDS technology.
Moreover, the difference source voltage of the source follower would result channel length modulation and it would make some extra voltage error in the output.
The operation of the voltage mode sensor pixel is described as following. First, the Vpd is reset to Vresetin by device Mreset. After a fixed integration period, Vpd would be discharged by the photocurrent of the photodiode and decreased from a high potential voltage to a low potential voltage. Then, the voltage of node Vpd would be transfer to Vout by the voltage buffer, the source follower implemented by Ms and current source, and then sampled in the following capacitor.
Figure 2.1 The general 3T voltage mode sensor pixel
The Fig. 2.2 shows another voltage mode pixel. It uses operation amplifier to replace the source follower as the voltage buffer, which is composed of a reset MOS (Mreset), a photodiode (sensor) and an operational amplifier (OP) with negative feedback as shown in Fig. 2.2. The operation equation of the amplifier in the Fig. 2.2 is shown as equation (2-3).
Figure 2.2 The voltage mode sensor pixel with OP
out pd
V = V
(2-3) Now let us analysis the two type voltage buffer. The gain of the source follower is shown in equation (2-4), and the unit gain buffer op is shown in equation (2-5).0.8 ~ 0.9
As shown in the equations (2-4) and (2-5), the OP structure provides higher gain than the source follower, therefore, the linearity of the OP structure is much better than that of source follower. Besides, the OP structure is not suffered from the body effect and the channel length modulation. It can achieve a better performance with the CDS technology compared to the source follower structure. The disadvantage of the OP voltage buffer is the input offset voltage; however, it can also be removed by the CDS technology operation. The analysis of CDS operation and the comparison of the two types of voltage buffers would be shown in the following.Figure 2.3 The general CDS operation circuit Fig. 2.3 shows the general CDS operation circuit and equation (2-6) is the output function of the Fig 2.3. For the source follower voltage buffer, the CDS operation is described as following equations. Vi : the voltage after integration
Vresetin: the reset voltage of the photodiode
VGS(Vt1), VGS(Vt2): the VGS during difference body effect
From equations (2-7), (2-8), and (2-9), we can find that the Vt variation of the active device cannot be reduced completely due to the body effect in the source follower case. For the operation amplifier voltage buffer, the CDS operation is described as following equations.
signal i os
V = − V V
(2-10)reset resetin os
V = V − V
(2-11)
V
o= − V
iV
resetin (2-12) From equations (2-10), (2-11) and (2-12), the OP structure as a voltage buffer shows a better performance in the CMOS voltage mode sensor application. It can provide higher gain and lower error, which results a better linearity and performance.Therefore, the OP structure pixel is implemented in our CMOS voltage mode sensor design. The compare of OP and source follower active device are shown in table II.
Fig. 2.4 shows the schematic of the implemented voltage mode image sensor circuit, which is composed of the sensor pixel and the correlated double sampling (CDS) readout circuit. The pixel is composed of a reset MOS (MR) and a photodiode.
The CDS readout circuit is composed of some switches (SHS, SHR, CE, Clamp, Col, Group Column), storage capacitors (Cs, Cr), CDS couple capacitors (Co_s, Co_r), and the current source pairs (Mb3s, Mb3r).
Figure 2.4 The 3T voltage mode sensor circuit
Fig. 2.5 shows the architecture of the operational amplifier in the Fig. 2.4, and Fig. 2.6 is the bias circuit of the amplifier. For low power consideration, the operational amplifier is biased at small dc current. The total dc current of the folded cascade amplifier is 24uA. The bias circuit of the folded cascade OP is designed to consume less dc current for low power, the total dc current of the bias circuit is 16uA.
The total power consumption of the folded cascode amplifier is 0.00013 W. The device dimensions of the folded cascode amplifier are shown in table III and the device dimensions of the bias circuit are shown in table IV.
Figure 2.5 The folded cascade amplifier
Figure 2.6 The bias circuit of folded cascade amplifier
The sensor readout operation of Fig. 2.4 is described as following and the control clock diagram is shown in Fig 2.7. First, the Vpd is reset to Vresetin by device MR. After a fixed period of integration time, the Vpd (Vsig) is readout by the voltage buffer, and is sampled in Cs (SHS is on) as shown in Fig. 2.8. It gives, The control signal Clamp is designed as being always on to keep M1 gate and M2 gate voltage in Vb2 during the sampling period of Cr and Cs. By using the designed Clamp operation, we can eliminate the charge injection and clock feedthrough non-ideal effect induced by the switches SHS and SHR.
Figure 2.7 The clock diagram of the voltage mode sensor
Figure 2.8 The sample-signal operation of voltage mode sensor
Figure 2.9 The sample-reset operation of voltage mode sensor
After signals being sampled to capacitors Cs and Cr, the switches controlled by signals “Group column” and “Col” are turned on. By turning off the switch controlled by “Clamp” and turning on the switch controlled by “CE”, the result is transferred to the nodes out_s and out_r as shown in Fig. 2.10. it gives,
_ arg
Vclamp_charge: the voltage variation result from charge injection and clock feedthrough
induced by switch clamp
VCE_charge: the voltage variation result from charge injection and clock feedthrough induced by switch CE
In the above equation, Vb2 is used to adjust the output common mode voltage by the level shift. The level shift is composed of Co_s, Cor, Mclamp1 and Mclamp2. Due to the design of the clock operation, the level shift wouldn’t increase extra error in the output. From equation (2-21), we can find that the charge injection and clock feedthrough of switches SHS and SHR are eliminated by the CDS operation.
Figure 2.10 The operation of voltage mode sensor with “Col” on, “Clamp” off, and
“CE” on,
By the way, the control signal “Group column” is designed to reduce the output loading of output nodes (Vout_s, Vout_r). The operation is described as below. In this work, there is 700 columns in the sensor array. If the control signal “Group column”
is not used in the circuit, there will be 700 pairs transmission gate in the output node during the readout period. In the optimized design as shown in Fig. 2.11 and Fig. 2.12, the control signal “Group column” was used in the readout circuit as grouping architecture. It shows there are only 53 pairs of transmission gate loading left in the output node by grouping design. The total loading, represented in number of transmission gates, depends on grouping architecture is shown as equation (2-22).
Number of transmisson gates
=
column number+
group number(2-22) By using the grouping architecture controlled by “Group column”, we can minimize the output loading and driving capability as well. Therefore, the power consumption is minimized and optimized in the readout circuit.Figure 2.11 The illustration of Group
Figure 2.12 The illustration of Group column
Operation amplifier
Source follower
Channel length modulation No Yes
Body effect No Yes
Offset voltage Yes No
Area Big Small
linearity High Low
Power
(in this design about 3 times)
High Low
Operation range
(if maximum reset voltage 2.8V )
1.3V~2.8V 1.3V~2.8V
(Vov=200mV)
Table II. The compare of two type active device
Name Type Single Finger
Size Multiply Total Size
M1 NMOS 2μm/1μm 1 2μm/1μm
M2 NMOS 2μm/1μm 1 2μm/1μm
M9 PMOS 4μm/2μm 6 24μm/2μm
M10 PMOS 4μm/2μm 6 24μm/2μm
M3 PMOS 2.4μm/1μm 3 7.2μm/1μm
M4 PMOS 2.4μm/1μm 3 7.2μm/1μm
M7 NMOS 2μm/2μm 1 2μm2μm
M8 NMOS 2μm/2μm 1 2μm/2μm
M5 NMOS 1μm/2μm 3 3μm/2μm
M6 NMOS 1μm/2μm 3 3μm/2μm
Mb NMOS 1μm/2μm 6 6μm/2μm
Table III. The dimensions of the folded cascode operational amplifier
Name Type Single Finger
Size Multiply Total Size
MB1 PMOS 2μm/2μm 2 4μm/1μm
Table IV. The dimensions of the folded cascode operational amplifier bias circuit