CHAPTER 6 CHIP IMPLEMENTATION
6.2 C OMPARISON WITH OTHER SIMILAR WORK
Up to now, there is no issue in IEEE publication about dual mode channel decoder implementation for 3GPP2 standard. Thus, we make a comparison with the unified channel decoder for 3GPP standard in [23] shown in Table 6.3. Due to lower code rate specified in both turbo mode and Viterbi mode, the gate count is larger than that of [23]. However, the proposed design is more economic in power dissipation as a whole.
Table 6.3 Comparison with other similar work
The proposed design [26] [23]
Technology 0.18 CMOS 0.18 CMOS
Compatible Standard 3GPP2 3GPP
Gate Count 115,000 85,000
Core Size 7.29 mm2 9 mm2
Supply Voltage 1.8V 1.8V
Maximum Clock Rate 100MHz 110.8MHz
Maximum Throughput Rate (Turbo Mode)
4.52 Mb/s with 6 iterations
2.5 Mb/s with 10 iterations 4.1 Mb/s with 6 iterations
Power (Turbo Mode)
Embedded Memory Size 251.64 Kb 239 Kb
6.3 Summary
In this chapter, a chip implementation result is presented. The turbo decoding is able to achieve a maximum data rate of 4.52Mb/s with relative lower power consumption. The Viterbi decoding consists of 256 states and uses the same datapaths as those of the turbo decoder. Various coding rates, including 1/2, 1/3, 1/4, and 1/6, are supported. As compared to the unified channel decoder in where 292mW is required to decode a 2Mb/s data stream with ten iterations, the proposed design is more efficient in power dissipation.
Chapter 7
Conclusion and Future Work
7.1 Conclusion
In this thesis, we talked about an implementation method for a dual mode Turbo/Viterbi decoder compatible for 3GPP2 standard. The chip is completed by verilog-HDL and UMC 0.18µm standard cell library. The chip die size is 3.40 x 3.40 mm2 with the core size of 2.70 x 2.70 mm2. It contains 115k gate counts of logic cell. The maximum iteration number for turbo decoding is fixed to six. With supply voltage of 1.8V, the power consumption in Turbo mode is about 83mW while working at 66MHz to achieve 3.1 Mb/s throughput rate; and that in Viterbi mode is about 25.1mW while working at 20MHz to achieve 1Mb/s throughput rate.
7.2 Future Work
Up to now, the early termination scheme is regarded as the most efficient way to reduce the power consumption in turbo decoders. It uses several characteristics in turbo decoding to judge if decoding sequence is nearly correct before maximum iteration number is achieved.
Once iterative decoding can be stopped earlier, then the power can be saved. In [24], an iteration stopping criterion has been devised based on the cross entropy between the a posteriori probabilities of two SISO decoders for each iteration. In [25], two further simplified criteria were proposed for cost down. Although the performance of our design in the aspect of power consumption listed in Table 6.2 is attractive, there is no early termination technique used in it. This may be an aspect that we can try to better our design.
Bibliography
[1] Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD), 3GPP TS 25.212, V3.11.0, Sep 2002
[2] Physical Layer Standard for cdma2000 Spread Spectrum Systems, 3GPP2 Std.
C.S0002-C, May 2002.
[3] C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon Limit Error-Correcting Coding and Decoding: turbo-codes,” in IEEE Int. conf. Communications (ICC), pp.1064-1070, May 1993.
[4] D.Divsalar, S. Dolinar, R. J. McEliece, and F. Pollara, “Performance Analysis of Turbo Codes,” in IEEE Military Communication conf., vol. 1, 5-8, pp. 91-96, Nov. 1995.
[5] J. Hagenauer and P. Hoeher, “A Viterbi Algorithm with Soft-decision Outputs and its Applications,” in IEEE GLOBE-COM, Dallas, TX, pp. 47.1.1-47.1.7, Nov. 1989.
[6] L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal Decoding of Linear Codes for Minimizing Symbol,” in IEEE Trans. Inform. Theory, no.IT-20, pp 284-287, Mar, 1974.
[7] J. H. Andersen, “‘Turbo’ Coding for Deep Space Application,” in IEEE International Symposium on Inform. Theory, 17-22, pp.36, Sep. 1995.
[8] J. H. Andersen, “Turbo codes extended with outer BCH code,” in Electronics Letters, vol. 32, no. 22, 24, pp.2059-2060, Oct. 1996.
[9] P. Robertson, E.Villebrun and P. Hoeher, “A Comparison of Optimal and Sub-optimal MAP Decoding Algorithms operating in the Log Domain,” Proc. ICC’95, Seattle, June 1995.
[10] J. Hagenauer, E. Offer, and L. Papke, “Iterative Decoding of Binary Block and Convolutional Codes,” IEEE Trans. Inform. Theory, vol. 42, no. 2, pp. 429-445, Mar.
1996.
[11] J. A. Erfanian, S. Pasupathy, and G.Gulak, “Reduced Complexity Symbol Detectors with Parallel Structures for ISI Channels,” IEEE Trans. Commun., vol. 42, no. 2/3/4, pp.1261-1271, Feb./Mar./Apr. 1994.
[12] T. A. Summers and S. G. Wilson, “SNR Mismatch and Online Estimation in Turbo Decoding,” IEEE Trans. Commun., vol. 46, pp.421-423, Apr. 1998.
[13] A. Worm, P. Hoeher, N. Wehn, “Turbo-Decoding Without SNR Estimation,” IEEE Commun. Letters, vol. 4, no. 6, pp.193-195, June 2000.
[14] S. A. Barbulescu, “Iterative decoding of turbo codes and other concatenated codes,”
University of South Australia, PhD Dissertation, Aug. 1995.
[15] S. A. Barbulescu, “On Sliding Window and Interleaver Design,” Electronics Letters, vol.
37, no. 21, pp.1299-1300, Oct. 2001.
[16] A. J. Viterbi, “Error bounds for convolutional codes and asymptotically optimum decoding algorithm,” IEEE Trans. Inform. Theory, vol. IT-13, no. 2, pp.260-269, Mar.
1973.
[17] Y. Wu and B. D. Woerner, “Internal data width in SISO decoding module with modular renormalization,” in IEEE Vehic. Tech. Conf., vol. 1, pp. 675-679, May 2000.
[18] Y. Wu, B. D. Woerner, and T. K. Blankenship, “Data Width Requirements in SISO Decoding With Module Normalization,” in IEEE Trans. On Commun., vol. 49, no. 11, pp. 1861-1868, Nov. 2001.
[19] T. K. Blankenship and B. Classon, “Fixed-Point Performance of Low-Complexity Turbo Decoding Algorithms,” in IEEE Vehic. Tech. Conf., vol. 2 pp. 1483-1487, May 2001.
[20] C. B. Shung, P. H. Siegel, G. Ungerboeck and H. K. Thapar, “VLSI architectures for metric normalization in the Viterbi algorithm,” IEEE International Conference on Communications, vol. 4, pp.1723-1728, Apr. 1990.
[21] A. P. Hekstra, “An Alternative to Metric Rescaling in Viterbi Decoders,” IEEE Trans.
Commun., vol. 37, no. 11, pp. 1220-1222, Nov. 1989.
[22] G. Feygin and P. G. Gulak, “Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi Decoder,” IEEE Trans. On Commun., vol. 41, no. 3, pp. 425-429, Mar. 1993.
[23] M. A. Bickerstaff, D. Garrate, T. Prokop, C. Thomas, B. Widdup, G. Zhou, L. M. Davis, G. Woodward, C. Nicol, R. H. Yan, “ A Unified Turbo/Viterbi Channel Decoder for 3GPP Mobile Wireless in 0.18-μm CMOS”, in IEEE Journal of Solid-State Circuits, vol.37, no.11, Nov. 2002
[24] M. Moher, “Decoding via Cross Entropy Minimization,” in Proc. IEEE Globecom Conf., Houston, TX, Dec. 1993, pp.809-813.
[25] R. Y. Shao, S. Lin, and M. P. C. Fossorier, “Two Simple Stopping Criteria for Turbo Decoding,” IEEE Trans. On Commun., vol. 47, no. 8, pp.1117-1120, Aug. 1999.
[26] C. C. Lin, Y. H. Shih, H. C. Chang, and C. Y. Lee, “A Dual Mode Channel Decoder for 3GPP2 Mobile Wireless Communications,” Proc. 30th Eur. Solid State Circuits Conf.
(ESSCIRC), 2004.
[27] 李鎮宜, 林建青, 施彥旭, “低複雜度之渦輪解碼器架構,” 中華民國專利申請中, 交 通大學申請案編號: 04(專)A015
作 者 簡 歷
姓名 ：施彥旭
出生地 ：台灣省彰化縣 出生日期：1980. 11. 4
學歷： 1986. 9 ~ 1992. 6 彰化縣立鹿港國民小學
1992. 9 ~ 1995. 6 彰化市私立精誠高級中學附設國中部 1995. 9 ~ 1998. 6 彰化市私立精誠高級中學
1998. 9 ~ 2002. 6 國立交通大學 電子工程系 學士
2002. 9 ~ 2004. 6 國立交通大學 電子研究所 系統組 碩士
得 獎 事 績
九十一學年度 第二學期電子研究所書卷獎
九十二學年度 全國大專院校 FPGA 系統設計競賽 Xilinx 研究所組特優 九十三學年度 斐陶斐榮譽學會新榮譽會員
發 表 論 文
Yew-San Lee, Cheng-Mou Yu, Hung-Kuo Wei, Yen-Hsu Shih, Chen-Yi Lee,
“A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication,” in IEEE ISCAS, May 2002.
Hung-Kuo Wei, Yew-San Lee, Yen-Hsu Shih, Chen-Yi Lee, “A novel fixed bit plane error resilient image coding for wireless multimedia transmission,” in IEEE ICIP, Sep. 2002.
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, and Chen-Yi Lee, “A Dual Mode Channel Decoder for 3GPP2 Mobile Wireless Communications,” in IEEE ESSCIRC, 2004