Performance Assessments
6.4 Chapter Summary
Applied with impressive dynamic boundary prediction scheme as well as the proposed low-power/high-performance methodology, our work supports dramatic power and rate-distortion superiority over prior studies, which has been summarized in average of 621.8µW of power dissipation with dynamic 198.8µW and more than half the bitrate improvement of equal frame PSNR compared to prior hardware-oriented full search, as from Figure 6.2 to Table 6.8.
Table 6.6: Power & rate-distortion assessments for the proposed memory architecture (CIF 30fps, QP = {36,42})
Static Scene Active Scene Sequence akiyo M&D foreman foreman mobile stefan
Frames 1–30 1–30 221–250 191–220 1–30 221–250
Motion local local global extreme global extreme Average
Co
re Total (µW) 483.0 493.7 615.7 680.6 601.9 856.2 621.8
Dyn. (µW) 60.0 70.7 192.7 257.6 178.9 433.2 198.8
Ref.buff
er Total (µW) 62.7 63.6 78.8 88.1 73.2 104.2 78.4
Dyn. (µW) 2.7 3.6 18.8 28.1 13.2 44.2 18.4
wrt. Total (core) 13.0% 12.9% 12.8% 12.9% 12.2% 12.2% 12.6%
wrt. Dyn. (core) 4.5% 5.0% 8.7% 10.9% 7.4% 10.2% 7.8%
SA
P Total (µW) 280.0 285.0 310.9 378.0 340.7 502.4 349.5
wrt. Total (core) 58.0% 57.7% 51.4% 55.5% 56.6% 58.7% 56.3%
Clo
ck Dyn. (µW) 33.25 36.97 73.71 94.94 63.41 112.60 69.1
wrt. Dyn. (core) 55.6% 52.4% 39.5% 36.9% 35.5% 26.1% 41.0%
Comp.Red.
ME skipped 70.3% 71.0% 33.1% 27.0% 12.9% 26.3% 40.1%
BWmem 81.1% 80.4% 76.7% 57.8% 77.7% 59.1% 72.1%
Op. rate 97.6% 97.3% 95.3% 84.5% 96.0% 85.9% 92.8%
R−
D ∆PSNR (dB) 0.076 0.065 0.054 -0.145 0.011 0.155 0.029
∆Rate (%) -1.76% -0.15% -8.86% -32.52% -2.58% -52.21% -17.35%
MasterThesis,NationalChiaoTungUniversity
Sequence QP
Core power Ref. buffer SAP array Clock tree SKIP BWmem Arithmetic Op. Rate-Distortion Total Dyn. D/T Total wrt. Total wrt. Total wrt. ratio Avg. Saving Avg. Saving ∆Rate ∆PSNR
(µW) (µW) (%) (µW) Core (µW) Core (µW) Core ratio (%) SA (%) SP (%) (%) (dB)
StaticScene
Akiyo CIF 36 487.8 64.8 13.3% 63.1 12.9% 282.0 57.8% 35.1 54.2% 65.3% 441.0 80.9% 26.9 97.5% 0.62% 0.062 42 478.2 55.2 11.5% 62.3 13.0% 278.0 58.1% 31.4 56.9% 75.3% 429.9 81.3% 24.4 97.8% -4.14% 0.089 Avg. 483.0 60.0 12.4% 62.7 13.0% 280.0 58.0% 33.2 55.6% 70.3% 435.5 81.1% 25.6 97.6% -1.76% 0.076 M&D CIF 36 500.2 77.2 15.4% 64.2 12.8% 288.1 57.6% 39.2 50.8% 68.2% 457.9 80.1% 30.9 97.2% -2.77% 0.075 42 487.2 64.2 13.2% 63.0 12.9% 281.8 57.8% 34.7 54.0% 73.7% 445.3 80.7% 27.5 97.5% 2.47% 0.054 Avg. 493.7 70.7 14.3% 63.6 12.9% 285.0 57.7% 37.0 52.4% 71.0% 451.6 80.4% 29.2 97.3% -0.15% 0.065 Foreman CIF 36 537.8 114.8 21.3% 67.1 12.5% 317.0 58.9% 48.7 42.4% 47.1% 526.5 77.1% 47.4 95.6% -2.40% 0.051 221–250 42 693.5 270.5 39.0% 90.5 13.0% 304.8 44.0% 98.7 36.5% 19.1% 549.2 76.2% 53.9 95.1% -15.32% 0.058 Avg. 615.7 192.7 30.2% 78.8 12.8% 310.9 51.4% 73.7 39.5% 33.1% 537.9 76.7% 50.6 95.3% -8.86% 0.054
ActiveScene
Foreman CIF 36 693.5 270.5 39.0% 90.5 13.0% 384.4 55.4% 98.7 36.5% 19.1% 980.9 57.4% 175.6 83.9% -34.31% −0.224 191–220 42 667.7 244.7 36.6% 85.7 12.8% 371.6 55.7% 91.2 37.2% 34.8% 964.9 58.1% 162.7 85.1% -30.73% −0.065 Avg. 680.6 257.6 37.8% 88.1 12.9% 378.0 55.5% 94.9 36.9% 27.0% 972.9 57.8% 169.1 84.5% -32.52% −0.145 Mobile CIF 36 601.4 178.4 29.7% 73.3 12.2% 340.3 56.6% 63.6 35.6% 9.1% 513.6 77.7% 44.0 96.0% -1.33% −0.003 42 602.3 179.3 29.8% 73.1 12.1% 341.1 56.6% 63.2 35.3% 16.6% 513.8 77.7% 43.7 96.0% -3.82% 0.024 Avg. 601.9 178.9 29.7% 73.2 12.2% 340.7 56.6% 63.4 35.5% 12.9% 513.7 77.7% 43.9 96.0% -2.58% 0.011 Stefan CIF 36 896.4 473.4 52.8% 110.1 12.3% 527.5 58.8% 120.0 25.3% 21.0% 963.3 58.2% 164.6 84.9% -53.56% 0.131 42 815.9 392.9 48.2% 98.4 12.1% 477.2 58.5% 105.2 26.8% 31.6% 921.5 60.0% 142.6 86.9% -50.86% 0.178 Avg. 856.2 433.2 50.5% 104.2 12.2% 502.4 58.7% 112.6 26.1% 26.3% 942.4 59.1% 153.6 85.9% -52.21% 0.155 Average 621.8 198.8 32.0% 78.4 12.6% 349.5 56.3% 69.1 41.0% 40.1% 642.3 72.1% 78.7 92.8% -16.35% 0.019
92
Chapter6.PerformanceAssessments NTU, Huang et al. NTU, Huang et al. Miyama et al. NTU, Lin et al. NTU, Chen et al.
This work ISCAS’03 [46] TCSVT’04 [65] JSSC’04 [32] ISCAS’04 [33,45] TCSVT’07 [31,37,47]
Processing
720 × 480@30fps CIF@30fps CIF@30fps CIF@30fps CIF@30fps CIF@30fps
Capability
Resolution Integer-pel Integer-pel Half-pel Integer-pel Integer-pel Integer-pel
Block Size 16 × 16 16 × 16 16 × 16, 8 × 8 16 × 16 16 × 16 ∼ 4 × 4 16 × 16 ∼ 8 × 8
Algortihm Full search Global Gradient Fast full search Fast full search
Fast full search
Elimination Decent (4SS) (4SS-based)
Search Center (0, 0) (0, 0) (0, 0) (0, 0) (0, 0) Adaptive
Technology 0.35µm 0.35µm 0.18µm 0.18µm 0.18µm 0.13µm
Voltage 3.3V 3.3V 1.2V 1.8V 1.3V 1.2V
Core Area 25.56µm2 27.8µm2 13.65µm2 2.2µm2 3.61µm2 0.69µm2
Internal Memory 24.6Kbits 24.1Kbits 40Kbits 24.1Kbits 64Kbits 11.5Kbits
Eqv. Gates
106Kgates 115Kgates 1000Kgates 137Kgates 300Kgates 96Kgates
(2-NAND)
Clock Rate 66.67MHz 27.8MHz 13.5MHz 48.67MHz 13.5MHz 20MHz
Power Consumption 737.32mW 189mW 12mW 8.46mW 4.38mW 0.62mW
Dynamic Power N/A 0.20mW
93
Conclusions
To reveal an impressive design methodology for portable video codec, this thesis thor-oughly treats design tradeoffs in motion estimation between rate-distortion, complex-ity, and power. Three most advanced power-efficiency techniques have been explored to achieve an excellent low-power, cost-efficiency, and high rate-distortion requirements for advanced motion estimation task.
A false rate constrained MB-skipping detection in use of likelihood ratio test has suc-cessively exploited the computation dependence and effectively eliminated the complexity burden. The proposed detection method moderately detects whether the current mac-roblock should be SKIP coding or not prior to motion estimation, where the 17%–87%
probability of detection is archived at false rate 1% relative to the motion activity.
Because of advanced prediction on intensive mathematics, motion estimation domi-nates computation and memory access complexity. To effectively release the power de-mand, prior studies was strictly exploited the characteristics of hardware acts in exces-sively compromising rate-distortion performance. In addition, measuring of power in high abstraction regardless dependance of architecture is generally insufficient. To illustrate, a biased block-matching scheme in use of dynamic boundaries is then preformed, which has been proven significantly improving arithmetic efficiency as well as motion-compensated fidelity. Simulation assessment shows that our method can save maximum 52.6% the coding bitrate efficiency, and release more than 90% arithmetic amount.
In reference buffer optimization, we theocratically give a perspective in optimizing memory structure using technology-dependent high-level power analysis methodology.
By applying the optimization methodology, the power dissipation of internal memory (register file) is successfully suppressed to 12% with respected to total core power and only 7.8% in dynamic power.
Moreover, three novel key techniques was first presented in this thesis are 1) low switching AD (absolute difference) logic (section 4.2), 2) shortest distance bus coding scheme (section 4.4), and 3) low-cost accumulator-structured MV cost computation logic
(section 4.5). These ingenious arithmetic simplifications or designs effectively advantages ours work as well.
As an excellent design methodology was applied in the implementation, the proposed design supports dramatically power and rate-distortion superiority over prior designs, which has been summarized in average of 621.8µW of power dissipation with dynamic 198.8µW and more than half the bitrate improvement of equal frame PSNR compared to prior hardware-oriented full search. In brief, the present work not only elegantly resolves the prior design gap between rate-distortion fidelity and power demanding, but also further regulates the design guideline for qualified low power video motion estimation, and has greatly encouraged the advancement to realized a real-time, low-cost, as well as high-performance video codec.
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