Chip Implementation

The proposed LDPC decoder was implemented with the 0.13 um 1P8M standard CMOS process. The chip layout of the LDPC decoder including the B2C memory, the shift size ROM table, ADDLL and the other control logic and processing blocks is shown in Fig. 4.16. The decoder die size is 13.69 um². The total gate count of the LDPC decoder is 1265K, where 194K is for B2C memory. We use 184 pins for pads and 67 pins for I/O pads and 114 pins for VDD/GND pads. The SRAM contains the B2C Memory and Channel Memory, and the ROM1 and ROM2 are the shift size rom table.

The post simulation result is tested to verify the functional correctness. The maximum iteration number is 20. The maximal data rate of the decoder is 28.3 Mb/s at typical case while working at 198MHz and 20.3 Mb/s at worst case. The power consumption is 700 mW.

This power consumption analyzes only on iteration decoding excluding receiving data and outputting result.

The throughput rate is mostly constrained by the cyclic shifters latency and the data bus bandwidth for message passing. Although we simplify the operation of iteration decoding, a lot of accessing memory operations makes our decoding latency longer.

SRAM

Shifter1

Shifter2

ROM2

ROM1

ADDLL

Fig. 4.18 Chip layout of the LDPC decoder chip

Table 4.1 Summary of the LDPC decoder chip

Technology Standard 0.13-um CMOS 1P8M

Core size 3.0 um × 3.0 um

Chip size 3.7 um × 3.7 um

Gate count 1265K

Power dissipation 700mW @ 198MHz *

Maximum data rate 20.3Mb/s @ 20iterations **

*： The simulation environment is set at typical speed corner (1.2V Supply voltage) and the power consumption analyzes only on the iteration decoding excluding receiving data and outputting result.

**： The simulation environment is set at worst speed corner (1.08V Supply voltage) with considering the coupling noise due to crosstalk effect on signal wires. The maximum data rate is 28.3Mb/s at typical case, the worst IR drop=0.04V.

Table 4.2 shows the gate count of each functional block, “Control + C2B Register” denotes the control logic for the whole decoder and the registers for C2B block storage.

Table 4.2 Gate count of functional block

Function Block Total gate count

Cyclic Shifter 135K

C2B Block 176K

B2C Block 37K

Control + C2B Register 758K

RAM 91K

ROM + Asynchronus 73K

Total 1270K

4.3 Comparison

The comparison of our proposed LDPC code decoder with state-of-the-arts are listed in Table

4.2.

Table 4.3 Comparison of LDPC chip

Proposed [24]

Block length 576~2304 (19 types) 1200

Code structure Irregular irregular

Code rate 1/2, 2/3, 3/4, 5/6 3/5

Silicon proven No Yes No

Technology 0.13-um 0.18-um 0.13-um

Supply voltage 1.2V 1.8V 1.2V

Clock freq. 142MHz 83MHz 145MHz

Chip size 13.69mm² 25mm² 13.47mm²

Gate count 1.265M 1.15M

Power dissipation 700mW@198MHz 644mW 299mW

Data rate 20.3Mb/[email protected] 3.33Gb/s 5.8Gb/s

Decoding iteration 20 8

Chapter 5 Conclusion and Future Work

5.1 Conclusion

In this thesis, we analyze the LDPC code for 802.16e based on the BER performance and propose an efficient architecture for 802.16e. In the proposed architecture we reschedule the process task for reducing memory usage and decreasing the latency. According our post simulation, this LDPC decoder can achieve the data rate to 20.3Mb/s using 0.13um, 1.08V, 1P8M CMOS process and the power consumption is 700mW at iterative decoding. The core occupies 3.0um×3.0um and the chip size is with 184 pins

5.2 Future Work

For our proposed architecture, the area for processing element is still too large, and the throughput rate is a little low to achieve the standard requirement. Our future work is to optimize the area and throughput rate. We will try to reuse the processing element to decrease the area and try to reschedule the processing element to achieve high clock rate.

References

[1] P. Elias, “Coding for noisy channels”, IRE. Conv. Rec. , pt.4, pp.37-47, 1955.

[2] I. S. Reed and G. Solomon, “Polynomial Codes over Certain Fields,” J. Soc. Ind. Appl.

Math., 8: 300-304, June 1960.

[3] C. Berrou and A. Glavieux, “Near optimum error correcting coding and decoding:

turbo-codes,” IEEE Trans. Commun., vol. 44, no. 10, pp. 1261-1271, Oct. 1996.

[4] R. G.. Gallager, “Low-Density Parity-Check Codes,” IRE Trans. Inform. Theory, vol.

IT-8, pp. 21-28, Jan. 1962.

[5] D. J. C. Mackay, “Good error-correcting codes based on very sparse matrices,” IEEE Trans. Inform. Theory, vol. 45, pp. 399-431, Mar. 1999.

[6] D. J. C. Mackay and R. M. Neal, “Near Shannon limit performance of low-density parity-check codes,” Electron. Lett., vol. 32, pp. 1645-1646, Aug. 1996.

[7] T. J. Richardson and R. L. Urbanke, “Efficient encoding of Low-Density Parity-Check codes,” IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 638-656, Feb. 2001.

[8] J. Pearl, Probabilistic Reasoning in intelligent systems: networks of plausible inference.San Mateo: Morgan Kaufmann, 1988.

[9] R. J. McEliece, D. J. C. MacKay, and J. F. Cheng, “Turbo decoding as a instanec of Pearl’s blief propagation algorithm,” IEEE J. Select. Areas Commun., vol. 16, no. 2, pp.

140–152, Feb. 1998.

[10] F. R. Kschischang and B. J. Frey, “Iterative decoding of compound codes by probability propagation in graphical models,” IEEE J. Select. Areas Commun., vol. 16, no. 2, pp.

219–230, Feb. 1998.

[11] J. L. Fan, Constrained coding and soft iterative decoding. Netherlands: Kluwer Academic, 2001.

[12] G. D. Forney, Jr., “Codes on graphs: Normal realizations,” IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 520–548, Feb. 2001.

[13] F. R. Kschischang, B. J. Frey, and H. A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 498–519, Feb. 2001.

[14] R. M. Tanner, “A recursive approach to low complexity codes,” IEEE Trans. Inform.

Theory, vol. IT-27, no. 5, pp. 399–431, Sept. 1981.

[15] D. B. West, Introduction to graph theory, 2nd ed. NJ: Prentice-Hall, 2001.

[16] J. L. Fan, Constrained Coding and Soft Iterative Decoding. Kluwer Academic Publishers, 2001

[17] A. Anastasopoulos, “A comparison between the sum-product and the min-sum iterative detection algorithms based on density evolution,” in IEEE GLOBECOM’01, vol. 2, Nov.

2001, pp. 1021 – 1025

[18] X. Y. Hu, Eleftheriou, D. M. Arnold, and A. Dholakia, “Efficient implementation of the sum-product algorithm for decoding ldpc codes,” in IEEE GLOBECOM’01, vol. 2, Nov.

2001, pp. 25–29

[19] H. S. Song and P. Zhang, “Very-low-complexity decoding algorithm for low-density parity-check codes,” in IEEE PIMRC’03, vol. 1, Sep. 2003, pp. 161 – 165

[20] J. Chen and M. P. C. Fossorier, “Near optimum universal belief propagation based decoding of low-density parity check codes,” IEEE. Trans. Commun., vol. 50, pp.

406–414, Mar. 2002

[21] H. Jun and K. M. Chugg, “Optimization of scaling soft information in iterative decoding via density evolution methods,” in IEEE. Trans. Commun., vol. 6, Jun. 2005, pp. 957 – 961.

[22] J. Chen and M. P. C. Fossorier, “Density evolution for two improved bp-based decoding algorithms of ldpc codes,” IEEE. Communications Letters, vol. 6, pp. 208 – 210, May 2002

[23] IEEE Standard for Local and metropolitan area networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands and Corrigendum 1, 2006.

[24] Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang and Chen-Yi Lee, “A 3.33Gb/s (1200,720) Low-Density Parity Check Code Decoder,” IEEE ESSCIRC, pp. 211 - 214 Sep. 2005.

[25] N.Wiberg, “Codes and decoding on general graphs,” Ph.D. dissertation, Univ. Linkoping, Sweden, 1996.

作 者 簡 歷

姓名: 嚴紹維

出生地: 台灣省高雄市 出生日期: 1982.7.29

學歷: 1988.9~1994.6 高雄市立四維國小 1994.9~1997.6 高雄市立五福國中 1997.9~2000.6 高雄市立高雄高級中學

2000.9~2004.6 國立交通大學 電子工程學系 學士 2004.9~2006.8 國立交通大學 電子研究所 系統組 碩士