Chip Summary

The chip summary is shown in Table 5-1. The square version is prepared to tape out from CIC, and the rectangular version is directly taped out from UMC. The cell library and PAD library is different between the two versions: square version’s library is from Faraday, and rectangular version’s is from UMC. As the results shown in Table 5-1, the square version’s working frequency can meet the system specification while the rectangular version’s can not. In summary, the taped out version chip size is 3955×2755 um², power consumption is 47.1 mW at 8.2/57.1 MHz, and is using UMC 90nm 1V CMOS process. Moreover, the area of two FFT/IFFT processors for FFT_ch/IFFT_ch blocks in DF DF-based CE in the taped out chip is 1.711 mm², and the power consumption of that is 20.2 mW working at 57.1 MHz.

Table 5-1 Chip summary

Item Specification

Square Version Rectangular Version (taped out)

FFT_ch/IFFT_ch Processors (taped out)

Technology UMC 90nm

CMOS 1P9M

Core 2411×2411 3144×1944

PAD Core 3057×3057 3799×2599

Area(um²)

Chip 3211×3211 3955×2755

1.711 mm²

Working Frequency 11.2/78.4 MHz 8.2/57.1 MHz 57.1 MHz Power Consumption

Chapter 6

Conclusion and Future Work

In this thesis, a FFT/IFFT processor with parallel-in-parallel-out in normal order which is used in a DF DFT-based channel estimation block is proposed. A 802.16e baseband receiver including this DF DFT-based channel estimation is taped out.

To design a FFT/IFFT processor with parallel-in-parallel-out in normal order, we analyze different parallel-in-parallel-out FFT architecture, and try to design the FFT/IFFT processor based on memory-based architecture. Memory allocation helps us to design a FFT/IFFT processor with parallel-in-parallel-out in normal order, and commutator design helps us to use single port memories to reduce the area of memories. These two methods can also be applied to different specification of parallel-in-parallel-out FFT processor. As the synthesis results, the proposed 1024-point FFT/IFFT processor can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 78.4 MHz, it consumes 21.7 mW with 155792 gates (including memory) that occupy 0.545 mm² by using 90 nm, 1V CMOS process.

A study of partial FFT for DF DFT-based channel estimation is also presented in this thesis. The pruning algorithm with only a subset of input or output points can help us to decrease the FFT processor hardware cost, and the multiple subsets of input or output points help us to save more power in FFT computation. As the analysis, the proposed partial FFT processor can reduce 75.1% of the memory size, 22.3% of the complex multipliers, and 30% of the complex adders as compared with traditional radix-2 SDF FFT architecture. Furthermore, with increasing the partial FFT control

for the proposed partial FFT processor, the proposed partial FFT can reduce maximum 65.3% of multiplication operations and 49.5% of addition operations, which may save more power if the 8 valid output point’s indices have common bits.

In the future, since we only implement the FFT/IFFT processor with parallel-in-parallel-out in normal order, a suitable FFT/IFFT processor for DF DFT-based channel estimation have to keep on study, such as the FFT/IFFT processor combining partial FFT algorithm and MIMO FFT concept.

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