Circuit Implementation

A UWB receiver front-end referenced to the band group #1 of the Multi-Band OFDM with operation frequency between 3GHz to 5GHz is designed for the goals of low noise figure, low power, high gain, and wide bandwidth. As shown in Figure 53, the high-Q bond wires are fully used to reduce the chip area and improve the noise figure in this design. The load inductor of the first stage is chosen to resonate at 3.1 GHz with capacitance at the drain node of the transistor M1, which includes the device parasitic and the capacitance between the bottom plate of C1 and ground. The load inductor of the second stage is chosen to generate a resonance at 4.6 GHz. The resonance frequencies of the first and second stages together cover

49

Figure 54. UWB receiver front-end circuit chip layout.

Figure 55. UWB receiver front-end PCB layout.

the 3-5-GHz bandwidth for UWB band group #1 applications.

The capacitance of capacitor C₁ is selected to be 4.92 pF for signal coupling and without suffering from severe parasitic. With simulation, the best gain flatness can be obtained while the value of capacitor C2 is 39.36 pF. Since the LNA and mixers are integrated on chip, the original buffer stage at the LNA output is no longer required.

Figure 54 shows the layout of the receiver front-end. The die area is much reduced since the bond-wires are fully used to replace most of the on-chip spiral inductors. The PCB layout is shown in Figure 55. The RF signal path is arranged with the shortest distance and the

50

Figure 56. Balun for LO quadrature output.

differential LO signals are routed symmetrically for both I and Q. The transformers of 4:1 Ohm ratio are to be installed on the board for differential IF converting to single ended-output.

Figure 56 shows the balun for LO quadrature output at 3960 MHz. The pattern is simulated with Momentum of Agilent ADS for 0°, 90°, 180°, and 270° outputs.

6.5 Simulation Results

The post-layout simulation was accomplished with Cadence SpectreRF simulator and Aglient ADS. Individual simulation of LNA and mixers are conducted first. As shown in Figure 57, a buffer circuit is added to the LNA for simulation. Figure 58 shows simulation setup and results of single mixer and two mixers in parallel. The individual simulations prepare for the integration of the LNA and mixers in the receiver front-end. Since there are three 528MHz-bands in the band group #1, each kind of test is run for all three bands. Figure 59 shows the double-sideband noise figure of the receiver is well below 3 dB. Since the receiver adopts direct-conversion architecture, the double-sideband noise figure is reasonable to represent the noise performance. The lowest conversion gain is 18dB as shown in Figure 60.

51

Figure 57. Individual simulation results of LNA circuit in RX package.

Figure 58. Individual simulation results of Mixer circuit in RX package.

52

Figure 59. RX Simulation results- noise figure (double-sideband)

Figure 60. RX Simulation results- conversion gain

The gain curve tends to fall with higher band for the input impedance at the RF port of the mixers is lower at higher frequency band. A buffer between the LNA and mixers can improve that, but suffers from additional power consumption. Since the noise figure of the receiver is well below the specification, the gain difference can be compensated with the succeeding variable gain amplifier. Two-tone signals with 4.125MHz spacing are applied to the receiver to observe the input referred third-order intercept point (IIP3). One-tone test is performed to obtain the input referred 1dB compression point (IP1dB). The simulated IIP3 is higher than –30.4 dBm and the simulated IP1dB is better than -46.7 dBm, respectively, as

53

Figure 61. RX Simulation results- IP2 and IP3 at band#1

Figure 62. RX Simulation results- P1dB at band#2

Figure 63. RX Simulation results- IP2 and IP3 at band#2

54

Figure 64. RX Simulation results- P1dB at band#2.

Figure 65. RX Simulation results- IP2 and IP3 at band#3.

Figure 66. RX Simulation results- P1dB at band#3.

55

Error Vector Magnitude of Band #2

-25 Error Vector Magnitude of Band #2

-25

Figure 67. Summary of RF/Baseband co-simulation.

Table 4. Power consumption details of receiver front-end

21.3

shown in Figure 61~66. The power dissipation of the whole receiver front-end including the output buffers is 21.3 mW as detailed in Table 4.

Figure 67 shows the summary of the circuit-level co-simulation of EVM with various input power of the receiver. The EVM goes higher as the input power goes below -90 dBm as well as above -65 dBm. The lower bound is limited by the sensitivity of the receiver and the upper bound by the linearity. Since the minimum sensitivity requirement of the band group #1 is -83.6 dBm, the receiver front-end can work well for this specification. When a complete version of algorithm-level of UWB baseband transceiver is available, the co-verification results will be closer to the real performance. Figure 68 shows a comparison of co-simulation results between the circuit-level RF front-end of this design and the behavior building block.

56 (a)

(b)

Figure 68. Comparison of co-simulation results: (a) with circuit-level RF front-end, (b) with behavior building block.

57

6.6 Summary

The proposed topology of low power UWB LNA with staggering tuning technique has been applied to the RF front-end for the UWB direct conversion receiver. The RF front-end performs low power, wide bandwidth and low noise. The system is verified by RF/baseband co-simulation. Implemented in 0.18-µm CMOS technology, the results demonstrate that the presented RF front-end is paving the way to a new generation of low power UWB applications. In addition, the design can be easily modified to fit other band groups of MB OFDM proposal.

58

Chapter 7 Conclusions

This thesis has presented a two-stage stacked topology employing staggering tuning technique for low power UWB LNAs. It has enabled the implementation of a 2.4-9.4 GHz low power LNA in a 0.18μm CMOS technology. This novel topology has been applied to the RF front-end for the UWB direct conversion receiver which performs low power, wide bandwidth and low noise. In conclusion, the key contributions presented in previous chapters are summarized below.

7.1 Summary

A two-stage stacked topology employing staggering tuning technique has been presented for low power UWB LNAs in Chapter 3. The quality factors for circuit design and inductor selection are discussed. In addition, design optimization for the power-constrained stacked amplifiers in wide bandwidth applications is also presented. The LNA is put in the UWB system for verification in Chapter 4. The LNA circuit implemented in 0.18-µm CMOS process shows a 2.4-9.4-GHz bandwidth in Chapter 5. The amplifier provides a maximum forward gain (S21) of 9.7 dB while drawing 7.3 mW from a 1.8-V supply. A noise figure as low as 4.17 dB and an IIP3 of –3.5 dBm have been measured. In chapter 6, the novel topology of low power UWB LNA has been applied to the RF front-end for the UWB direct

59

conversion receiver. In the RF front-end, a wideband passive mixer is designed for the purpose of low power little flicker noise and high linearity after the LNA. A baseband amplifier biased at ground level is designed with consideration of low noise for compensating the gain loss of the passive mixer and consequently help improving overall noise performance of the receiver. The UWB receiver front-end referenced to the band group #1 of the Multi-Band OFDM with operation frequency range 3-5 GHz demonstrates low noise figure, low power, high gain, and wide bandwidth. It is also verified by a RF/Baseband co-simulation.