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The combination with IMF and LT buffer

4.1 Buffer layer and isolation improvement

4.1.5 The combination with IMF and LT buffer

Due to the high sensitivity and variation in growing the quantum dot, we decide to add an AlSb LT buffer layer, which is insensitive to the chamber condition, as illustrated in Fig 4- 17.

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Fig 4- 17 Schematic of the buffer layer combines the IMF array and LT method

Fig 4- 18 The LT-AlSb pair

From the previous experiment, the roughness is the most drawback of LT buffer.

Trying to solve this problem, we adjust the thickness of LT layer and cap a layer with normal temperature on it for smoothing, as shown in Fig 4- 18.

Rs (Ω/□) Ns (cm-2) Mobility (cm2V-1s-1)

Rn927 346 7.95 x 1011 22700

Rn928 375 8.86 x 1011 19200

Table 4- 1 The results of Hall measurement in the samples Rn927 and Rn928

After a series of work, we obtain high mobility in sample Rn927 and Rn928, as shown in Table 4- 1, which is about 20000cm2V-1s-1.

Rn927, 928

AlSb

GaAs substrate Al0.7Ga0.3Sb 300nm

Active layer

AlSb IMF quantum dots

LT-AlSb pairs }1.1um

AlSb

LT - AlSb

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4.2 Channel design

The improvement of mobility and sheet resistances in Table 4- 2 indicates that we have approached the epitaxy of LT buffer layer. The other evidence is the buffer leakage. Fig 4- 19 shows the buffer leakage of Rn927 is less than 10nA, which is very small. So the next step is the channel design.

0.0 0.2 0.4 0.6 0.8 1.0

Fig 4- 19 The buffer leakage of Rn927

Fig 4- 20 Schematic of the structure with different active layer

Fig 4- 20 is the schematics of the device structure with different active layer. The detailed channel design and SnTe doping condition is shown in Table 4- 2. With the

Rn9xx

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thickest InAs layer in Rn927, its mobility is the highest and agrees with our expectation. Compared with Rn927, the other two samples Rn936 and Rn938 have small proportion of InAs. So their mobility is a little lower than Rn927 but still close to 15000cm2V-1s-1.

x/y/z thickness (nm) SnTe doping Rs (Ω/□) Ns (cm-2) Mobility (cm2V-1s-1)

Rn927 3/9/3 300°C 346 7.95 x 1011 22700

Rn936 3/6/6 325°C 450 8.68 x 1011 15000

Rn938 3/6/6 350°C 550 8.96 x 1011 12700

Table 4- 2 The results of Hall measurement in the samples with different active layer

The device I-V curves of Rn927 with 2um gate length are shown in Fig 4- 22 and Fig 4- 22. According to Fig 4- 21, the device leakage is near 80mA/mm at Vd=1V, Vg=-1.2V. But Fig 4- 22 indicates that the gate leakage is only 6mA/mm at this condition. As a result, the device leakage doesn’t come from the gate.

0.0 0.2 0.4 0.6 0.8 1.0

0 40 80 120 160

200 Rn927, A4 Vg, top= 0.1V step=-0.1V bottom=-1.2V Lg=2um W=50um

Id (mA/mm)

Vds (V)

Fig 4- 21 The drain characteristics of Rn927

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Fig 4- 22 The gate leakage of Rn927

The device I-V curves of Rn936 with 2um gate length are shown in Fig 4- 24 and Fig 4- 24. The device leakage is near 60mA/mm at Vd=1V, Vg=-0.7V.

Compared with the gate leakage showing in Fig 4- 24 which is less than 5mA/mm, the device leakage is still serious.

0.0 0.2 0.4 0.6 0.8 1.0

Fig 4- 23 The drain characteristics of Rn936

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Fig 4- 24 The gate leakage of Rn936

The same situation occurs in Rn938. The device I-V curves of Rn936 with 2um gate length are shown in Fig 4- 26 and Fig 4- 26. The device leakage is near 60mA/mm at Vd=1V, Vg=-1.1V. The gate leakage showing in Fig 4- 26 is less than 15mA/mm, so the device leakage doesn’t come from gate, either.

0.0 0.2 0.4 0.6 0.8 1.0

Fig 4- 25 The drain characteristics of Rn938

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Fig 4- 26 The gate leakage of Rn938

We attributed the difference from the Al0.7Ga0.3Sb buffer layer. This layer is used as a passivation layer for AlSb. If the resistance of this layer is lower than AlSb buffer, it may be a leakage path, as shown in Fig 4- 27.

Fig 4- 27 Schematic of the parallel resistance existing in buffer

As a result, more negative gate bias is needed to pinch off the drain current. This means the threshold voltage is changed by the Al0.7Ga0.3Sb layer. However, the threshold voltage (Vt) would become so negative that the Schottky gate couldn’t afford it. As Fig 4- 26 shows, the maximum gate leakage is near 12mA/mm at Vd=

1V and Vg= -1.1V and would increase dramatically.

Rn938

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To improve the operation of devices, we try to remove the Al0.7Ga0.3Sb layer. The SnTe doping temperature is 400°C and the whole epitaxy structure is shown in Fig 4- 28.

Fig 4- 28 Schematic of the structure without the Al0.7Ga0.3Sb layer

We compare the Hall data after the Al0.7Ga0.3Sb buffer was removed, as shown in Table 4- 3. The sheet resistance increases with the removal of the Al0.7Ga0.3Sb layer from 550Ω/□ to 980Ω/□, indicates that this layer may help to improve the roughness in channel. The degradation of sheet resistance would also affect the mobility in

Table 4- 3 The comparison of the basic parameters with and without the Al0.7Ga0.3Sb layer

The results of the HEMT with 2um of gate length are presented as followings.

Fig 4- 29 shows the drain current Id from Vd=0V to 1.2V in Rn953. The contact resistance of this device is 0.5Ω-mm. The gate leakage is shown in Fig 4- 30 correspondingly. According to these two figures, the devices could be nearly pinch-off

Rn953

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with threshold voltage = -0.9V and meanwhile, the gate leakage is about 6mA/mm, accounting for a large proportion of the drain current at this region. This is the first time for us to achieve pinch off in devices operation.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Fig 4- 29 The drain characteristics of Rn953 with 2um of gate length

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Fig 4- 30 The Schottky gate leakage of Rn953

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Fig 4- 31 shows the enhancement in drain current and transconductance with the increase of drain voltage. The threshold voltage of this device is about -0.8V. The peak value of transconductance (Gm) is 730mS/mm, occurring at a very high drain voltage 1.6V, and the gate voltage -0.55V. The Schottky gate would suffer too large electric field and breakdown with the voltage above it.

Rn953, C21

Fig 4- 31 Measured DC transconductance of Rn953

0.1 1 10

Fig 4- 32 Measured RF characteristic of Rn953

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The values of ft and fmax of a device with 2um gate-length is shown in Fig 4- 32, which are 6GHz and 8GHz.

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