Complexity Analysis

Each^_a_ncan be calculated in linear time since the system matrix of (3.7) is a lower triangular matrix. After each^_a_nhas been calculated, the statistical temperature profile can be extracted as E{T (˜ξ)} = E{^_a₁φ₁(˜ξ) + · · · +^_a_mφ_m(˜ξ)}, (3.8) V ar{T (˜ξ)} = V ar{^_a₁φ₁(˜ξ) + · · · +^_a_mφ_m(˜ξ)}. (3.9) Fig. 3.4 is the simulating algorithm,SETS, of the proposed simulator. As discussion in sec-tion 3.1, Phase 2 is the part needed to re-perform when design is changed. Phase 1 is related to the technology node and unchanged as used the simulator under the same process.

3.4 Complexity Analysis

In this section, the complexity of Phase 2 in Fig. 3.4 is analyzed. The temperature profile over the chip is analyzed into P Q blocks, where P and Q have the same definitions in section 3.3.

Equally, the power profile is also approximated by these blocks. According to [18], the com-plexity of the deterministic thermal solver used in this work is O(P Q log₂N_xN_y), where N_x

Algorithm Statistical-Electro-Thermal-Simulation (SETS)

Input: Leakage power cell library, Chip Design, and spatial correlation model Output: statistical temperature profile E{T^∗{ ˜ξ}} and V ar{T^∗{ ˜ξ}}

Phase 1

1 Parse input files

2 Applying Karhunen-Lo`eve expansion to transform the spatially correlated process parameters

3 Construct the sampling points by Smolyak sparse formula.

Phase 2

4 For each sampling point ˜ξⁱ ∈ ˜ξ 5 do Electro-Thermal-Coupling

6 Solve unknown coefficients of Newton form of polynomial interpolation by equation (3.7) 7 E{T^∗{ ˜ξ}} and V ar{T^∗{ ˜ξ}}

∗ denotes the distributed values over a chip.

Fig. 3.4: Simulating algorithm of the proposed statistical electro-thermal simulator.

and N_y are the truncated number of bases in x- and y-direction, respectively, and these are far less than the number of blocks P Q. Because leakage power is highly correlated by temperature, it is updated by Leakage-power-updating algorithm in Fig. 3.2. In line 4 of Fig. 3.2, because process-variation grids are determined by process rather than the circuit, the grids are usually orders of number less than that of temperature blocks; the temperature blocks are finer than variation grids. It also shows that most of temperature blocks have only one process-variation grid inside. Therefore, since there are N_typetypes, in worst case, of functional gates in each process-variation grid over all temperature blocks, the complexity of updating leakage power for P Q blocks is O(P QN_type). In general, N_type is determined by the number and the spatial proportion of functional types in the circuit, and it is far less than the number of blocks P Q, too. To find the worst extreme bound of complexity, N_type in one temperature block of such process-variation grid can be simulated as a cumulative counts of functional types sorted area in an increasing series. It is referred to the maximum N_type is occurred when functional types having smallest area are gathered into one temperature block. For the previous discus-sion, the computational complexity of one electro-thermal loop from line 5 to line 6 in Fig. 3.2 is O(P Q log₂N_xN_y) + O(P QN_type). The iteration of electro-thermal coupling is based on the converging criterion and initial temperature setting. According to our experiment with sam-pling knots constructed by Monte Carlo method, the average count of iteration loop in Fig. 3.2

is less than 5. The converging criterion of the experiment is set as the temperature value for all blocks are less than 0.5% differing from the value in previous loop, and all the initial tem-perature values are set as room temtem-perature. We conclude that the computational complexity of electro-thermal coupling algorithm is O(rP Q(log₂N_xN_y+ N_type)), where r is the count of average electro-thermal coupling loop.

The simulating algorithm of the proposed statistical electro-thermal simulator is shown in Fig. 3.4. Phase 2 is the part needed to be recomputed as circuit design changing. In line 6, because the calculation of equation (3.7) is without the computation of matrix inverse and the matrix size is dependent on the number of sampling points m, the coefficients of it can be ob-tained in linear time. Since each sampling point needs to enter the electro-thermal coupling algorithm and the statistical temperature profile can be extract in linear time of line 7, the com-plexity of the proposed simulator is O(mrP Q(log₂N_xN_y + N_type)).

Chapter 4

Experimental Results

The developed statistical electro-thermal simulator is implemented in C++ language and tested on a Linux system with Intel Xeon 3.0-GHz CPU and 32 GB memory.

The die size is 2.5 mm × 2.5 mm × 0.5 mm. The junction depth is 20nm which is the nominal value for the 65nm technology [19]. The floorplan of test chip which having 1.2 million functional gates is shown as Fig. 4.1(a), and the geometries of chip and package are shown in Fig. 4.1(b). By applying the modeling skill of thermal parameter and iterative 1-D thermal computation scheme [17], the equivalent heat transfer coefficients of the primary and secondary heat flow paths, and thermal conductivity are 12000 W/(m·^◦C), 2017 W/(m·^◦C), and 148.13 W/(m·^◦C), respectively. The boundary condition of each vertical surface is set to be isothermal [18].

The nominal values of channel length and oxide thickness are 65nm and 1.5nm, respec-tively. The 3σ_Lch and 3σ_Tox are set to 12% and 5% of nominal values, respectively. Both η_y/L_y and η_x/L_xare set to 0.98 which means the correlation between two devices located half of the chip dimension away in the x-direction or the y-direction is 0.6. The temperature profiles is analyzed in 128 × 128 blocks and the process-variation grids is set as 10 × 10 grids. The setting of deterministic thermal simulator with truncated number of basis in x- and y-direction are both 32 which can reach higher accuracy than author’s recommend in [18].