In the Table 5-7, operands have the following meanings:
Operand Description
destination/src1 Destination register is also source register 1 destination Destination register
immediate Immediate value src1,src2 Source registers
Table 5-7: Computational Instruction Formats
Description Op-code Operand
Add with Overflow add destination, src1, src2 Add without Overflow addu destination, src1, src2
AND and destination, src1, immediate
Divide Signed div destination/src1, immediate
Divide Unsigned divu
Exclusive-OR xor
Multiply mul
Multiply with Overflow mulo Multiply with Overflow Unsigned mulou
NOT OR nor
OR or
Set Equal seq
Set Greater sgt
Set Greater/Equal sge
Set Greater/Equal Unsigned sgeu Set Greater Unsigned sgtu
Set Less slt
Set Less/Equal sle
Set Less/Equal Unsigned sleu
Set Less Unsigned sltu
Set Not Equal sne
Subtract with Overflow sub Subtract without Overflow subu
Remainder Signed rem
Remainder Unsigned remu
Chapter 5
Rotate Left rol
Rotate Right ror
Shift Right Arithmetic sra
Shift Left Logical sll
Shift Right Logical srl
Absolute Value abs destination,src1
Negate with Overflow neg destination/src1 Negate without Overflow negu
NOT not
Move move destination,src1
Multiply mult src1,src2
Multiply Unsigned multu
Trap if Equal teq src1, src2
Trap if not Equal tne src1, immediate
Trap if Less Than tlt
Trap if Less than, Unsigned tltu Trap if Greater Than or Equal tge Trap if Greater than or Equal, Unsigned
tgeu Table 5-7: Computational Instruction Formats
Description Op-code Operand
Chapter 5
Table 5-8: Computational Instruction Formats for mips3 Architecture Only
Description Op-code Operand
Doubleword Add with Overflow dadd destination,src1, src2 destination/src1,src2 Doubleword Add without Overflow daddu destination,src1, immediate
destination/src1, immediate Doubleword Divide Signed ddiv
Doubleword Divide Unsigned ddivu
Doubleword Multiply dmul
Doubleword Multiply with Overflow
dmulo Doubleword Multiply with
Overflow Unsigned
dmulou Doubleword Subtract with
Overflow
dsub Doubleword Subtract without
Overflow
dsubu Doubleword Remainder Signed drem Doubleword Remainder Unsigned dremu Doubleword Rotate Left drol Doubleword Rotate Right dror Doubleword Shift Right Arithmetic dsra Doubleword Shift Left Logical dsll Doubleword Shift Right Logical dsrl
Doubleword Absolute Value dabs destination,src1 Doubleword Negate with
Overflow
dneg destination/src1 Doubleword Negate without
Overflow
dnegu
Doubleword Multiply dmult src1, src2
Doubleword Multiply Unsigned dmultu src1, immediate
Chapter 5
Computational Instruction Descriptions
Table 5-9: Computational Instruction Descriptions
Instruction Name Description
Absolute Value (abs)
Computes the absolute value of the contents of src1 and puts the result in the destination register. If the value in src1 is –2147483648, the machine signals an overflow exception.
Add with Overflow (add)
Computes the twos complement sum of two signed values. This instruction adds the contents of src1 to the contents of src2, or it can add the contents of src1 to the immediate value. Add (with overflow) puts the result in the destination register. When the result cannot be extended as a 32-bit number, the machine signals an overflow exception.
Add without Overflow (addu)
Computes the twos complement sum of two 32-bit values. This instruction adds the contents of src1 to the contents of src2, or it can add the contents of src1 to the immediate value. Add (without overflow) puts the result in the destination register. Overflow exceptions never occur.
AND (and) Computes the Logical AND of two values. This instruction ANDs (bit-wise) the contents of src1 with the contents of src2, or it can AND the contents of src1 with the immediate value. The immediate value is not sign extended. AND puts the result in the destination register.
Divide Signed (div) Computes the quotient of two values. Divide (with overflow) treats src1 as the dividend. The divisor can be src2 or the immediate value. The instruction divides the contents of src1 by the contents of src2, or it can divide src1 by the immediate value. It puts the quotient in the destination register. If the divisor is zero, the machine signals an error and may issue a break instruction. The div instruction rounds toward zero. Overflow is signaled when dividing –
2147483648 by –1. The machine may issue a break instruction for divide-by-zero or for overflow. Note: The special case div $0,src1,src2 generates the real machine divide instruction and leaves the result in the hi/lo register. The hi register contains the remainder and the lo register contains the quotient. No checking for divide-by-zero is performed.
Divide Unsigned (divu)
Computes the quotient of two unsigned 32-bit values. Divide (unsigned) treats src1 as the dividend. The divisor can be src2 or the immediate value. This instruction divides the contents of src1 by the contents of src2, or it can divide the contents of src1 by the immediate value. Divide (unsigned) puts the quotient in the destination register. If the divisor is zero, the machine signals an
exception and may issue a break instruction. See the note for div concerning $0 as a destination. Overflow exceptions never occur.
Exclusive-OR (xor) Computes the XOR of two values. This instruction XORs (bit-wise) the contents of src1 with the contents of src2, or it can XOR the contents of src1 with the immediate value. The immediate value is not sign extended. Exclusive-OR puts the result in the destination register.
Move (move) Moves the contents of src1 to the destination register.
Chapter 5
Multiply (mul) Computes the product of two values. This instruction puts the 32-bit product of src1 and src2, or the 32-bit product of src1 and the immediate value, in the destination register. The machine does not report overflow. Note: Use mul when you do not need overflow protection: it’s often faster than mulo and mulou.
For multiplication by a constant, the mul instruction produces faster machine instruction sequences than mult or multu instructions can produce.
Multiply (mult) Computes the 64-bit product of two 32-bit signed values. This instruction multiplies the contents of src1 by the contents of src2 and puts the result in the hi and lo registers (see Chapter 1). No overflow is possible. Note: The mult instruction is a real machine language instruction
Multiply Unsigned (multu)
Computes the product of two unsigned 32-bit values. It multiplies the contents of src1 and the contents of src2 and puts the result in the hi and lo registers (see Chapter 1). No overflow is possible. Note: The multu instruction is a real machine language instruction.
Multiply with Overflow (mulo)
Computes the product of two 32-bit signed values. Multiply with Overflow puts the 32-bit product of src1 and src2, or the 32-bit product of src1 and the immediate value, in the destination register. When a overflow occurs, the machine signals an overflow exception and may execute a break instruction.
Note: For multiplication by a constant, mulo produces faster machine instruction sequences than mult or multu can produce; however, if you do not need overflow detection, use the mul instruction. It’s often faster than mulo.
Multiply with Overflow Unsigned (mulou)
Computes the product of two 32-bit unsigned values. Multiply with Overflow Unsigned puts the 32-bit product of src1 and src2, or the product of src1 and the immediate value, in the destination register. This instruction treats the multiplier and multiplicand as 32-bit unsigned values. When an overflow occurs, the machine signals an overflow exception and may issue an break instruction.
Note: For multiplication by a constant, mulou produces faster machine
instruction sequences than mult or multu can reproduce; however, if you do not need overflow detection, use the mul instruction. It’s often faster than mulou.
Negate with Overflow (neg)
Computes the negative of a value. This instruction negates the contents of src1 and puts the result in the destination register. If the value in src1 is –
2147483648, the machine signals an overflow exception.
Negate without Overflow (negu)
Negates the integer contents of src1 and puts the result in the destination register. The machine does not report overflows.
NOT (not) Computes the Logical NOT of a value. This instruction complements (bit-wise) the contents of src1 and puts the result in the destination register.
NOT OR (nor) Computes the NOT OR of two values. This instruction combines the contents of src1 with the contents of src2 (or the immediate value). NOT OR complements the result and puts it in the destination register.
Table 5-9: Computational Instruction Descriptions
Instruction Name Description
Chapter 5
OR (or) Computes the Logical OR of two values. This instruction ORs (bit-wise) the contents of src1 with the contents of src2, or it can OR the contents of src1 with the immediate value. The immediate value is not sign extended. OR puts the result in the destination register.
Remainder Signed (rem)
Computes the remainder of the division of two unsigned 32-bit values. The machine defines the remainder rem(i,j) as i–(j*div(i,j)) where j · 0. Remainder (with overflow) treats src1 as the dividend. The divisor can be src2 or the immediate value. This instruction divides the contents of src1 by the contents of src2, or it can divide the contents of src1 by the immediate value. It puts the remainder in the destination register. The rem instruction rounds toward zero, rather than toward negative infinity. For example, div(5,–3)=–1, and rem(5,–
3)=2. For divide-by-zero, the machine signals an error and may issue a break instruction.
Remainder Unsigned (remu)
Computes the remainder of the division of two unsigned 32-bit values. The machine defines the remainder rem(i,j) as i–(j*div(i,j)) where j · 0. Remainder (unsigned) treats src1 as the dividend. The divisor can be src2 or the immediate value. This instruction divides the contents of src1 by the contents of src2, or it can divide the contents of src1 by the immediate value. Remainder (unsigned) puts the remainder in the destination register. For divide-by-zero, the machine signals an error and may issue a break instruction.
Rotate Left (rol) Rotates the contents of a register left (toward the sign bit). This instruction inserts in the least-significant bit any bits that were shifted out of the sign bit.
The contents of src1 specify the value to shift, and the contents of src2 (or the immediate value) specify the amount to shift. Rotate Left puts the result in the destination register. If src2 (or the immediate value) is greater than 31, src1 shifts by (src2 MOD 32).
Rotate Right (ror) Rotates the contents of a register right (toward the least-significant bit). This instruction inserts in the sign bit any bits that were shifted out of the least-significant bit. The contents of src1 specify the value to shift, and the contents of src2 (or the immediate value) specify the amount to shift. Rotate Right puts the result in the destination register. If src2 (or the immediate value) is greater than 32, src1 shifts by src2 MOD 32.
Set Equal (seq) Compares two 32-bit values. If the contents of src1 equal the contents of src2 (or src1 equals the immediate value) this instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Set Greater (sgt) Compares two signed 32-bit values. If the contents of src1 are greater than the contents of src2 (or src1 is greater than the immediate value), this instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Set Greater/Equal (sge)
Compares two signed 32-bit values. If the contents of src1 are greater than or equal to the contents of src2 (or src1 is greater than or equal to the immediate value), this instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Table 5-9: Computational Instruction Descriptions
Instruction Name Description
Chapter 5
Set Greater/Equal Unsigned (sgeu)
Compares two unsigned 32-bit values. If the contents of src1 are greater than or equal to the contents of src2 (or src1 is greater than or equal to the immediate value), this instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Set Greater Unsigned (sgtu)
Compares two unsigned 32-bit values. If the contents of src1 are greater than the contents of src2 (or src1 is greater than the immediate value), this
instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Set Less (slt) Compares two signed 32-bit values. If the contents of src1 are less than the contents of src2 (or src1 is less than the immediate value), this instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Set Less/Equal (sle) Compares two signed 32-bit values. If the contents of src1 are less than or equal to the contents of src2 (or src1 is less than or equal to the immediate value), this instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Set Less/Equal Unsigned (sleu)
Compares two unsigned 32-bit values. If the contents of src1 are less than or equal to the contents of src2 (or src1 is less than or equal to the immediate value) this instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Set Less Unsigned (sltu)
Compares two unsigned 32-bit values. If the contents of src1 are less than the contents of src2 (or src1 is less than the immediate value), this instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Set Not Equal (sne) Compares two 32-bit values. If the contents of scr1 do not equal the contents of src2 (or src1 does not equal the immediate value), this instruction sets the destination register to one; otherwise, it sets the destination register to zero.
Shift Left Logical (sll)
Shifts the contents of a register left (toward the sign bit) and inserts zeros at the least-significant bit. The contents of src1 specify the value to shift, and the contents of src2 or the immediate value specify the amount to shift. If src2 (or the immediate value) is greater than 31 or less than 0, src1 shifts by src2 MOD 32.
Shift Right Arithmetic (sra)
Shifts the contents of a register right (toward the least-significant bit) and inserts the sign bit at the most-significant bit. The contents of src1 specify the value to shift, and the contents of src2 (or the immediate value) specify the amount to shift. If src2 (or the immediate value) is greater than 31 or less than 0, src1 shifts by the result of src2 MOD 32.
Shift Right Logical (srl)
Shifts the contents of a register right (toward the least-significant bit) and inserts zeros at the most-significant bit. The contents of src1 specify the value to shift, and the contents of src2 (or the immediate value) specify the amount to shift. If src2 (or the immediate value) is greater than 31 or less than 0, src1 shifts by the result of src2 MOD 32.
Table 5-9: Computational Instruction Descriptions
Instruction Name Description
Chapter 5
Subtract with overflow (sub)
Computes the twos complement difference for two signed values. This instruction subtracts the contents of src2 from the contents of src1, or it can subtract the contents of the immediate from the src1 value. Subtract puts the result in the destination register. When the true result’s sign differs from the destination register’s sign, the machine signals an overflow exception.
Subtract without overflow (subu)
Computes the twos complement difference for two 32-bit values. This instruction subtracts the contents of src2 from the contents of src1, or it can subtract the contents of the immediate from the src1 value. Subtract (without overflow) puts the result in the destination register. Overflow exceptions never happen.
Trap if Equal (teq) Compares two 2-bit values. If the contents of src1 equal the contents of src2 (or src1 equals the immediate value), a trap exception occurs.
Trap if not Equal (tne)
Compares two 32-bit values. If the contents of src1 do not equal the contents of src2 (or src1 does not equal the immediate value), a trap exception occurs.
Trap if Less Than (tlt)
Compares two signed 32-bit values. If the contents of src1 are less than the contents of src2 (or src1 is less than the immediate value), a trap exception occurs.
Trap if Less Than Unsigned (tltu)
Compares two unsigned 32-bit values. If the contents of src1 are less than the contents of src2 (or src1 is less than the immediate value), a trap exception occurs.
Trap if Greater than or Equal (tge)
Compares two signed 32-bit values. If the contents of src1 are greater than the contents of src2 (or src1 is greater than the immediate value), a trap exception occurs.
Trap if Greater than or Equal Unsigned (tgeu)
Compares two unsigned 32-bit values. If the contents of src1 are greater than the contents of src2 (or src1 is greater than the immediate value), a trap exception occurs.
Table 5-9: Computational Instruction Descriptions
Instruction Name Description
Chapter 5
Table 5-10: Computational Instruction Descriptions for mips3 Architecture Only
Instruction Name Description
Doubleword Absolute Value (dabs)
Computes the absolute value of the contents of src1, treated as a 64-bit signed value, and puts the result in the destination register. If the value in src1 is -2**63, the machine signals an overflow exception.
Doubleword Add with overflow (dadd)
Computes the twos complement sum of two 64-bit signed values. The instruction adds the contents of src1 to the contents of src2, or it can add the contents of src1 to the immediate value. When the result cannot be extended as a 64-bit number, the machine signals an overflow exception.
Doubleword Add without overflow (daddu
Computes the twos complement sum of two 64-bit values. The instruction adds the contents of src1 to the contents of src2, or it can add the contents of src1 to the immediate value. Overflow exceptions never occur.
Doubleword Divide Signed (ddiv)
Computes the quotient of two 64-bit values. ddiv treats src1 as the dividend.
The divisor can be src2 or the immediate value. It puts the quotient in the destination register. If the divisor is zero, the machine signals an error and may issue a break instruction. The ddiv instruction rounds towards zero. Overflow is signaled when dividing -2**63 by -1. Note: The special case ddiv $0,src1,src2 generates the real machine doubleword divide instruction and leaves the result in the hi/lo register. The hi register contains the quotient. No checking for divide-by-zero is performed.
Doubleword Divide Unsigned (ddivu)
Computes the quotient of two unsigned 64-bit values. ddivu treats src1 as the dividend. The divisor can be src2 or the immediate value. It puts the quotient in the destination register. If the divisor is zero, the machine signals an exception and may issue a break instruction. See note for ddiv concerning $0 as a destination. Overflow exceptions never occur.
Doubleword Multiply (dmul)
Computes the product of two values. This instruction puts the 64-bit product of src1 and src2, or the 64-bit product of src1 and the immediate value, in the destination register. The machine does not report overflow. Note: Use dmul when you do not need overflow protection. It is often faster than dmulo and dmulou. For multiplication by a constant, the dmul instruction produces faster machine instruction sequences than dmult or dmultu can produce.
Doubleword Multiply (dmult)
Computes the 128-bit product of two 64-bit signed values. This instruction multiplies the contents of src1 by the contents of src2 and puts the result in the hi and lo registers. No overflow is possible. Note: The dmult instruction is a real machine language instruction.
Doubleword Multiply Unsigned (dmultu)
Computes the product of two unsigned 64-bit values. It multiplies the contents of src1 and the contents of src2, putting the result in the hi and lo registers. No overflow is possible. Note: The dmultu instruction is a real machine language instruction.
Chapter 5
Doubleword Multiply with Overflow (dmulo)
Computes the product of two 64-bit signed values. It puts the 64-bit product of src1 and src2, or the 64-bit product of src1 and the immediate value, in the destination register. When an overflow occurs, the machine signals an overflow exception and may execute a break instruction. Note: For multiplication by a constant, dmulo produces faster machine instruction sequences than dmult or dmultu can produce; however, if you do not need overflow detection, use the
Computes the product of two 64-bit signed values. It puts the 64-bit product of src1 and src2, or the 64-bit product of src1 and the immediate value, in the destination register. When an overflow occurs, the machine signals an overflow exception and may execute a break instruction. Note: For multiplication by a constant, dmulo produces faster machine instruction sequences than dmult or dmultu can produce; however, if you do not need overflow detection, use the