Chapter 3 Sandwich Ping-Pong Memory
3.4 Control Unit Circuit
We make up the Sandwich Ping Pong Memory with two parts, a Ping Pong Memory and a Common Bar. We build a control unit circuit to turn the original signals and addresses into those for Sandwich Ping Pong Memory (SPPM). Saving area is our destination and we do save the area of Ping Pong Memory actually. We could save the area of Ping Pong Memory;
however, we gained the area of the control unit circuit. Therefore, the less area we used for control unit circuit, the more area we saved in Sandwich Ping Pong Memory.
Idle WE Addr_W>12 Addr_W>12 WE_Ping WE_Pong WE_CMB
0 0 0 0 0 1 X
1 1 1 0 0 X 0
1 1 1 1 X X X
Table 3.1 Signals and Addresses for 32bit SPPM with Common Bar 1X4
Table 3.1 shows the signals for 32-bit SPPM with Common Bar 1 X 4. We define the address for writing or reading is 0 to 15. When they are bigger than 12, the common bar is on operation. The inputs of it are WE, Addr_W and Addr_R represented the original signals of Write Enable, Address for Writing and Address for Reading, respectively. Its outputs are the WE_Ping, WE_Pong and WE_CMB represented the signals of Write Enable for Ping Memory, Pong Memory and Common Bar. It seems that we are using a Ping Pong Memory. In fact, we are using a Sandwich Ping Pong Memory. Figure 3.21 shows the signals and addresses transformed by the control unit circuit.
Figure 3.21 Signals and addresses for Sandwich Ping Pong Memory
We synthesize a control circuit with HDL. When the size of Common Bar is 1 x 8K, the gate count of the control circuit is 216 gate counts, shown in figure 3.22.
Figure 3.22 The gate count of control unit for Common Bar
M N P X Total 16 512 14 16 128K 131040 111104 45.877 114688 238 114450 16 512 15 16 128K 131056 119040 47.594 122880 223 122657 16 512 16 16 128K 131072 126976 49.206 131072 210 130862
Table 3.2 Data sheet for a Sandwich Ping Pong Memory
Table 3.2 is a data sheet for the Sandwich Ping Pong Memory in size 128K. It shows the control unit size of the different Common Bar in the Sandwich Ping Pong Memory. Every control unit is under three hundred gate counts. Figure 3.23 shows the Common Bar and Area Saved. Figure 3.24 shows the relationship between area saved and throughput reduction of the Sandwich Ping Pong Memory in the size 128k
Figure 3.23 Common Bar and Area Saved
Figure 3.24 Area Saved vs. Throughput Reduction
Chapter 4 Test Algorithm
Semiconductor memories have invented for decades and have been designed, produced, tested by customers all over the world. The test algorithms have been studied for decade years. [13]~
[23] It has been said that “memory testing is simple.” In fact, it is logistically simple about memory testing. The complex part of memory testing is the numerous ways that a memory would fail. Patterns are the essence of memory testing. However, there is no single pattern is sufficient to test a memory for all defect types. There are many algorithms had been proposed such as, Zero-One, Checker, March, GALPAT, Butterfly, etc…. Table 4.1 lists the required test time as a function of the algorithm complexity and the memory size.
Algorithm complexity
This chapter introduces popular memory fault models and many March algorithms. For Sandwich Ping-Pong Memory, we show a modified March C- algorithm for testing. The testing time is shorten and with high fault coverage.
4.1 Fault Models
This section gives a formal definition for the most popular fault models.[24] First, we introduce the notation used to represent the fault models are listed here:
0: Denotes that a cell is in logical state 0.
1: Denotes that a cell is in logical state 1.
? : Denotes that a cell is in logical state, which means “don’t care.”
↑ : A raising cell transition or denotes a write 1 operation to a cell containing a 0.
↓ : A falling cell transition or denotes a write 0 operation to a cell containing a 1.
b: Either a rising or falling cell transition.
∀ : denotes any operation; ∀ {0,1, , , }∈ ↑ ↓ b
< I / F >: denotes a fault in a single cell. I describes the condition for sensitizing the fault, F describes the value of the faulty cell. I∈{0,1, , , }↑ ↓ b , andF∈{0,1}.
The most popular fault models are listed as follows:
Stuck-at fault (SAF ): The logic value of a stuck-at (SA) cell or line is always 0 ( a stuck-at-0 fault, SA0 ) or 1 ( a stuck-at-1 fault, SA1 ).
Transition fault ( TF ): The cell or line which fails to transit from 0 to 1 (a <↑/0> TF ) or from 1 to 0 ( a <↓ > TF ). /1
Inversion coupling fault ( CFin ): An transition (↑ or ↓ ) in one cell inverts the content of another cell.
Idempotent coupling fault ( CFid ): An transition (↑ or ↓ ) in one cell forces the content of another cell to a certain value , 0 or 1.
State coupling fault ( CFst ): A coupled cell is forced to a certain value only if the coupling cell is in a given state.
Stuck-open fault ( SOF ): The cell fails to be accessed or a broken word/bit line.
Address decoder fault ( AF ): It is a functional fault in the address decoder that results in one of the following four cases shown in figure 4.1.
Fault A: With a certain address, no cell will be accessed.
Fault B: A certain cell is never accessed.
Fault C: With a certain address, multiple cells are accessed.
Fault D: A certain cell can be accessed with multiple addresses.
Figure 4.1 Different types of address decoder faults
4.2 March Algorithms
The simplest tests which detect SAFs, TFs and CFs are called ‘marches’. A March test is composed of a finite sequence of March elements. A March element is a finite sequence of write/read operations applied to every cell in memory before proceeding to the next cell. The address sequence can be either an increasing (⇑ ) address order (e.g. from address 0 to address N-1), or a decreasing (⇓ ) address order which is the opposite of the⇑ address order.
A write/read operation can be (wa), (wa), (ra), and (ra) where a is the background pattern and a is the inverted background pattern; a∈{0,1}; (wa) means “write the cell/word a”; (wa) means “write the cell/word a”; (ra) means “read a expected cell/word
a”; (ra) means “read a expected cell/word a.” A March algorithm example is shown in figure 4.2, and its flow is depicted in figure 4.3. Once the fault simulation is complete (all faults have been emulated), the fault coverage can be determined for the set of test vectors.
The fault coverage, FC, is a quantitative measure of the effectiveness of the set of test vectors in detecting faults, and in it most basic form is given by:
FC D
= T (4-1) Where D is the number of detected faults and T is the total number of faults in the fault list.
For design verification, the fault coverage can not only give the designer a rough quantitative measure of how well the design has been exercised, but also the undetected fault list can provide valuable information on those sub-circuits that have not been exercised as thoroughly as other sub-circuits.
Although example will be used in which the ⇑ address order goes from address 0, 1, 2. . . n-2 to n-1, this is not strictly necessary. It is necessary that the address-orders ⇑ and ⇓ are each other’s invert. For instance, when the address-orders ⇑ is chosen for some reason to be:
1, 0, 7, 5, 6 ,4 ,2 ,3 ; the address order ⇓ has to be:3, 2, 4, 6, 5, 7, 0, 1.This means that the march test { ( 1, 0); ( 0, 1)}⇑ r w ⇓ r w has the same fault coverage as the test { ( 1, 0); ( 0, 1)}⇓ r w ⇑ r w .
In Table 4.2, we show some popular March algorithms. And we also show the fault coverage in Table 4.3.
Figure 4.2 A March algorithm example
Figure 4.3 The procedure for the March algorithm example
Name Algorithm
Element Faults Detected
MATS++ c( 0); ( 0, 1); ( 1, 0, 0)w ⇑ r w ⇓ r w r SAF/AF March X c( 0); ( 0, 1); ( 1, 0) ( 0)w ⇑ r w ⇓ r w c r AF/SAF/TF/CFin March Y c( 0); ( 0, 1, 1); ( 1, 0, 0) ( 0)w ⇑ r w r ⇓ r w r c r AF/SAF/TF/CFin March C- { ( 0); ( 0, 1); ( 1, 0); ( 0, 1); ( 1, 0); ( 0)}c w ⇑ r w ⇑ r w ⇓ r w ⇓ r w c r SAF/AF/TF/CF
Table 4.2 Some March algorithms
Fault MATS++ March X March Y March C-
SAF 100% 100% 100% 100%
TF 100% 100% 100% 100%
SOF 100% 0.2% 100% 0.2%
AF 100% 100% 100% 100%
CFin 75.0% 100% 100% 100%
CFid 37.5% 50.0% 50.0% 100%
CFst 50.0% 62.5% 62.5% 100%
Table 4.3 Fault coverage of some popular March algorithms
4.3 A Test Algorithm for Sandwich Ping-Pong Memory
4.3.1 March C- Algorithm
March C- algorithm in Figure 4.4 satisfies the conditions of detecting simple (unlinked) faults such as SAFs, TFs, CFs, AFs, and SOFs [5]. This section shows a modified March C- algorithm in Figure 4.5 which is derived from March C- and proofs fault detection capabilities.
{ ( 0); ( 0, 1); ( 1, 0); ( 0, 1); ( 1, 0); ( 0)} c w ⇑ r w ⇑ r w ⇓ r w ⇓ r w c r M0 M1 M2 M3 M4 M5
Figure 4.4March C- algorithm
Condition March element 1
⇑ r ( ,..., x w x )
2
⇓ r ( ,..., x w x )
Table 4.4 Conditions for detecting address decoder faults
March C- satisfies the Conditions 1 and 2 for Address Faults in Table 4.4 [2]. When x =0 by means of March elements M2 and M5, when x =1 by means of March elements M3 and M4.
March C- will detect SAFs and TFs because all cells are read in states 0, 1, 0 … Thus, both
↑ and ↓ transitions, and read operations after them, have taken place. March C- will also detect idempotent and inversion coupling faults, with the restriction that these coupling faults are unlinked.
A fault is linked when that fault may influence the behavior of other faults. A fault is unlinked when that fault does not influence the behavior of other faults. Here is an example, as shown below.
Example
Suppose that there are two coupling faults in a memory, as shown in Figure 4.5. The first fault is that cell i is <↑ > coupled to cell j ; the second fault is that cell ;1 k is coupled to celll. The March test { ( 0); ( 0, 1); ( 0, 1); ( 1)}c w ⇑ r w c w w c r will detect both faults if i≠k (Figure 4.5(a)). The <↑ > CF will be detected by the ‘r0’ operation of March element, ;1 when operating on cell i . The <↑ > CF will be detected by the ‘r1’ operation of the last ;0 March element, when it operates on cellk.
However, this test will not detect the combination of the faults which occurs when i≡k (Figure 4.5(b)). The ‘link’ between the faults (in this case the effect that the coupled cells are the same) can cause the test not to find any fault; this effect is called masking. The ‘r0’
operation of the march element ( 0, 1)⇑ r w will not detect the linked CF because when operation on cell i the cell will contain a 0 value due to the <↑ > CF. The ‘r1’ operation ;0 of the last march element will not detect the linked CF because, when operating on cell i , it will contain a 1 value due to the <↑ > CF sensitized by the march element ;1 c( 0, 1)w w when it operates on cell j .
The following test has been designed to detect the faults of Figures 4.5(a) and 4.5(b):
{ ( 0); ( 0, 1); ( 0, 1); ( 1, 0, 1)}c w ⇑ r w c w w c r w w . The <↑ > CF of Figure 4.5(a) will be ;1 detected by the ‘r0’ operation of March element ( 0, 1)⇑ r w when it operates on cell i ; the CF of Figure 4.5(a) will be detected by the ‘r1’ operation of the last March element when it operates on cellk. The linked fault of Figure 4.5(b) will be detected by the ‘r1’ operation of the last March element when it operates on cell i .
Figure 4.5 Masking of coupling faults
The proof that March C- is complete is given below:
z AFs are detected because the conditions of in Table 4.3.
z SAF1 faults are detected by the read operations of M1, M2, M4, and M6.
z SAF0 faults are detected bye the read operations of M3, M5, and M7.
z Unlinked /0<↑ > TFs are detected by M1 followed by M2 or by M3 followed by M4.
z Unlinked /1<↓ > TFs are detected by M2 followed by M3 or by M4 followed by M5.
z Unlinked CFins <↑ ↑> are detected by M3 followed by M4; CFins ; <↓ ↑> are ; detected by M4 followed by M5.
z Unlinked CFids <↑ > are detected by M3 followed by M4; CFids ;0 <↑ > are ;1 detected by M1; CFids <↓ > are detected by M2; CFids ;0 <↓ > are detected by M4 ;1 followed by M5.
4.3.2 The Modified March C- Algorithm
There are two memory arrays which are called Ping memory (or Block A) and Pong memory (Block B) in a Ping Pong memory, introduced in Section 3.1.1. We have derived an algorithm for testing Ping memory and Pong memory simultaneously. We named this algorithm the Modified March C- shown in figure 4.5. In addition, the modified March C- is depicted carefully in figure 4.6, the upper sequence is testing the Block A memory array, meanwhile, the lower one is testing the Block B memory array.
There are two more March elements (M1 and M6) in this algorithm than in March C- algorithm. However, the fault coverage of this algorithm is the same as the one of March C- algorithm. Because these two March elements (M1 and M5) are nop (no operation) operations needed to be inserted into the March algorithm. As a result, the total operations increase.
There are eight operations within the algorithm, the test length of the modified March C- is eight, i.e. total 8N read and write operations are need to apply the algorithm (N is the memory size).
The modified March C- will detect CFins and CFids as shown below.
{ ( 0); ( 0); ( 0, 1);c w c r ⇑ r w ⇑( 1, 0);r w ⇓( 0, 1); ( 1, 0); ( 0); ( 0)}r w ⇓ r w c r c w M0 M1 M2 M3 M4 M5 M6 M7ٛ
Figure 4.6 Modified March C- algorithm
0 1 0 1 0 0 1 1 0 0 1 1 1 1 1
Figure 4.7 Modified March C- algorithm for block A and block B memory arrays
4.3.3 Testing of Sandwich Ping-Pong Memory
We will present how to test the Sandwich Ping-Pong Memory in this section. It is the modified March C- algorithm that we use for testing because it shows the high fault coverage.
It can test the most popular the faults such as: SAFs, TFs, AFs, CFins, CFids, and CFsts and its fault coverage was already presented in table 4.2.
When testing the Sandwich Ping-Pong Memory, the basic and simple way is to separate it into two parts: one is ping-pong memory and another is single port memory, in figure 4.8.
There is no doubt that the modified March C- algorithm can test not only the Ping Pong memory but also the Common Bar.
Figure 4.8 Test flow
Modified March C- satisfies the conditions 1 and 2 for AFs of Table 4.3: when x = 0 by means of March elements M2 and M5, when x =1 by means of March elements M3 and M4.
Modified March C- will detect SAFs and unlinked TFs because all cells are read in states 0, 1, 0, . .. . Thus, both ↑ and ↓ transitions, and read operations after them, have taken place.
Modified March C- will also detect idempotent and inversion coupling faults, with the restriction that these coupling fault are unlinked. The detection capabilities for idempotent and inversion coupling faults are proved below.
Idempotent coupling faults
The proof that the modified March C- detects CFids is split into two cases: 1. faults with the addresses of the coupling cells lower than the coupled cell, and 2. faults with the address of the coupling cells higher than the coupled cell. The coupled cell will be denoted byC , and i (one of) the coupling cells withC . As a reminder of the notation:i C is coupled to i C means j that an ↑ transition in C causes a o value inj C . i
Figure 4.9 Addresses of coupling and coupled cells
Case 1:
Let C be coupled to any number of cells with address lower than i, and let i C be the j highest of those cells (j<i), see figure 4.8. Four cases, corresponding to the four different types of CFids, can be distinguished: a.<↑ > , b.;0 <↑ > , c.;1 <↓ > , and d. ;0 <↓ > . These ;1 cases are proved below.
(a) If C is i <↑ > coupled to ;0 C , then the fault will be detected in march element M4 j followed by M5. See in figure 4.10 (a).
z In M4 a 1 is written in C and due to the j <↑ > coupling fault ;0 C will contain a i 0.
z In M5 a read operation is performed on C and a 0 instead of a 1 is read. i
z Linked CFids will not be detected. For example, C must not be i <↑ > coupled ;1 to cells with a lower address than j, because M4 operates on them after C . In that j case a 1 would be read in M5 which is the expected value. Thus, the fault would not be detected.
(b) If C is i <↑ > coupled to ;1 C then the March element M2 will detect the fault. See in j figure 4.10 (b).
z First a 0 will be read fromC , then a 1 will be written. Due to the j <↑ > coupling ;1 fault C will be forced to contain a 1. i
z A 1 instead of a 0 is read when M2 operates onC . i
(c) If C is i <↓ > coupled to ;0 C then he march element M3 will detect the fault. The j proof is similar to above.
(d) If C is i <↓ > coupled to ;1 C then the March elements M5 followed by M6 will j
detect the fault. C must not be i <↓ > coupled to cells with addresses lower than j. The ;1 proof is similar to above.
Figure 4.10 Detecting CFids
Case 2:
Let C be coupled to any number of cells with addresses higher than i and let i C be the j lowest addressed cell of them (j>i). The proof is similar to Case1, whereby M2 should be replaced by M4, M3 by M5, M4 by M2, M5 by M3 and M6 by M4.
Above it has been shown that modified March C- will detect CFids. The CFids must be unlinked, because not all combinations of faults are allowed, as proved above.
Inversion coupling faults Case 1:
Let C be coupled to any number of cells with addresses lower than i and let i C be the j
highest of those cells (j<i). Then, there are two cases, corresponding to eh two different types of CFins: <↑ >;b and<↓ >;b . These cases are proven below.
(a) C is i <↑ >;b coupled to C ; then M1 will detect the fault, as well as M4 followed j
by M4.
z M4 operates on C , making an j ↑ transition and inverting the contents of C ; i when M5 is operated on C a 0 instead of a 1 will be read. i
Figure 4.11 Detecting CFins
(b) C is i <↓ >;b coupled to C ; then M3 as well as M4 followed by M6 will detect j
the fault. The proof is similar to above.
Case 2:
The proof for j>i is similar to above.
As a result, we can use the modified March C- algorithm to test the Sandwich Ping Pong Memory. The fault coverage is at 100% for the stuck-at fault, transition fault, address fault, and coupling fault.
Chapter 5 Chip Implementation
We implement our Ping Pong memory in Full-Custom Design by specifying the layout of each individual transistor and the interconnections. Figure 5.1 shows the design flow for 64-byte Ping Pong Memory.
Figure 5.1 Design flow for 64-byte Pig Pong Memory
In order to be more flexible, we also complete the part of the Sandwich Ping Pong Memory,
Common Bar, and the test circuit by means of HDL (Hardware Description Language) which could synthesize the circuit we want. We show the results on Sparan-3 Starter board which provides a powerful, self-contained development platform. It features a 200K gate Sparten-3, on-board I/O devices, and two large memory chips.
5.1 Chip Implementation of the Sandwich Ping Pong Memory
5.1.1 The architecture of a Ping-Pong buffer
We have presented a double buffer roughly and realized that its application is in the 2-D DCT architecture in chapter 2. In this section, we are going to introduce the architecture of a double buffer, also known as, Ping-Pong buffer which is shown in figure 5.2.
Figure 5.2 Components in the Ping-Pong Memory
5.1.2 The detail design of a Ping-Pong buffer
A Ping-Pong buffer consists of the following kinds of component:
Memory cell
From the begging of introducing a Ping-Pong buffer, we talk about the basic component – the memory cell [27]. A memory cell can be implemented as SRAM, DRAM, and Flash. We take a six-device SRAM memory cell, also called CMOS SRAM cell shown in figure 5.3, as our memory cell. The load devices are PMOS enhancement mode transistors Q2 and Q4.
Comparing to the depletion mode NMOS as the load devices, this further reduces the power requirements of the cell; except for some small leakage current, no power will be dissipated during the time the cell retains the stored logic value. The transistors Q5 and Q6 work as switches and are named access transistors. When the gate of Q5 and Q6 are activated, they are turned-on and the memory cell work.
The operations of a memory cell are the following steps. When some word line is chosen, the access transistors are on and connect the two bit lines Q and Q . At this moment, we can write/read some data into/from the memory cell. On the operation of writing, it is easy to understand that the data (the voltage on bit lines) can be stored and latched between two back-to-back CMOS. On the opposite, the operation of reading, we turn down the voltage of word line after the data (voltage on the gate of CMOS) is passed to the bit lines from the memory cell. Finally, the data (voltage on the bit lines) is forward to the next component.
Figure 5.3 Six-device SRAM memory cell
Sense Amplifier, Equalization, and Pre-charge circuit
When the data (voltage) is on the bit lines, they will bump into the next component - Sense Amplifiers. Memory cells are composed by CMOS, so are the sense amplifiers. In figure 5.4, we show the differential sense Amplifier, equalization, and pre-charge circuit.
The sense amplifier is the most critical component in a memory chip. Sense amplifiers are
The sense amplifier is the most critical component in a memory chip. Sense amplifiers are