Cost Function

We construct a cost function cost(F ) = area(F ) + a*wire(F ), where F is the foorplan, area(F ) is the total area of executed blocks,a is a user given weight, and

wire(F ) is the total wire length of F measured by the half-perimeter estimation.

Chapter 4

Experimental Results

We proposed an more effective method of obtaining large-scale block placement satisfying the given symmetry constraints , and compare our result in our approach with [6] and [4]. Here we implemented our algorithm in the C++ programming language in Intel Pentium4 2.8GHz CPU with 2.0GB memory. (1) In comparing to paper [6] with symmetry constraints, the experimental results are implemented on an Intel(R) Xeon(TM) CPU 3.00GHz work station with 2GB memory. (2) In comparing to paper [4] with symmetry constraints, we implement their method by changing our set of moves in traditional way. For a reasonable compare, we valuate between Intel Pentium and Intel(R) Xeon(TM) by an easy program. The ratio of speed of Intel Pentium to Intel(R) Xeon(TM) about 1:1.06. Table 4.1 shows the results of this set of experiment. We compare the dead space with approximate simulation time. The third shows the number of symmetry groups and 5 symmetry groups with 8, 7, 7, 4 and 6 blocks respectively. Notice that the data is assign randomly.

In our approach, we can find that we have a more effective result when the total blocks are increased. When the block numbers increase up to 220, we have a smaller dead space in our approach than that in [6].For the data set of D220,considering the speed of machines, our simulation time will be divided 1.06 time,and the data of time and the time is 21 m. 1.6 s. and the space is 12.08 percent in [4] and the time

Table 4.1: Experimental comparisons between the results of our approach(Pentium4 2.8GHz) and [4](Xeon(TM) 3.00GHz)

Data Block Symmetry Our Approach [4]

Set No. Constraints Time Dead Space(%) Time Dead Space(%)

D50 50 8,7,7,4,6 66s 19.41 74.5s 4.28

D70 70 9,4,9,5,9 2m 10.1s 17.08 2m 12.9s 5.07

D100 100 4,12,4,11,12 4m 38s 16.85 4m 58.2s 8.48

D120 120 5,4,4,7,8 6m 34s 13.03 6m 15.2s 8.49

D170 170 8,7,7,4,6 13m 35.3s 12.69 13m 5.9s 10.14

D220 220 8,7,7,4,6 20m 48.3s 11.84 21m 1.6s 12.08

Figure 4.1: D120 with 120 blocks and 5 symmetry groups at Table 4.1 with our approach

is 19m. 57.9s. and the space is 11.84 percent in our approach. However, we can not compile the program of [6] when block numbers is over 250. Figure 4.1 shows the placement of D120 in Table 4.1.

Beside, we add our approach by changing our set of moves in traditional way as shown in Table 4.2. We also run it in the similar simulation time to compare its dead space. We can find it is not effective due to a too short simulation time for this approach. We take about 1 hour to simulate our programming and Figure 4.2 shows the results.

Table 4.2: Experimental comparisons between the results of our approach(Pentium4 2.8GHz) and similar program in [4](Pentium4 2.8GHz)

Data Block Symmetry Our Approach [6]

Set No. Constraints Time Dead Space(%) Time Dead Space(%)

D50 50 8,7,7,4,6 66s 19.41 65s 35.23

D70 70 9,4,9,5,9 2m 10.1s 17.08 2m 8.4s 34.25

D100 100 4,12,4,11,12 4m 38s 16.85 4m 48s 35.61

D120 120 5,4,4,7,8 6m 34s 13.03 6m 39s 32.01

D170 170 8,7,7,4,6 13m 35.3s 12.69 13m 10.3s 25.61

D220 220 8,7,7,4,6 20m 48.3s 11.84 20m 30.3s 24.32

Indeed, we do not run the linear program for symmetry constraints every iter-ation. And when the size of floorplan becomes larger, the effect of the symmetry groups becomes smaller. We offer an effective way to deal with the large floorplan applied in VLSI designs now.

Figure 4.2: D220 with 220 blocks and 5 symmetry groups about 1 hour with dead space of 9.93 percent with our approach

Chapter 5

Conclusion and Future Work

In this thesis, we proposed an more effective method of obtaining large-scale block placement satisfying all the given symmetry constraints. This algorithm has an efficient trend to get a nearly optimum solution and when the sizes of the floorplan become larger, the effect of the symmetry groups becomes smaller. We offer an effective way to deal with the large floorplan applied in VLSI designs now.

Our future problem is experiments on industrial applications of analog circuits.

Even it is useful and helps to speed up the automation of analog layout designs with symmetry constraints.

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