Digital Control Oscillator

The proposed DCO is a behavior model. The basis frequency is 333 MHz. Each step of DCO is 10fs.

Chapter 4

The proposed SDPLL Software

4.1. OPENRISC ISA Overview

The OPENRISC instruction set which shows in Fig. 4.1 includes the following principal features. First, Simple and uniform-length instruction formats featuring five Instruction Subsets. Second, OPENRISC Basic Instruction Set (ORBIS32/64) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 32-bit and 64-bit data.

Third, OPENRISC Vector/DSP eXtension (ORVDX64) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 8-, 16-, 32- and 64-bit data. Last, OPENRISC loating-Point eXtension (ORFPX32/64) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 32-bit and 64-bit data. The Table 4.1 shows difference between subsets. The proposed of SDPLL uses ORBIS32 to be instruction set.

Fig. 4.1 OPENRISC instruction set ORBIS32 32-bit instructions

ORBIS64 64-bit instructions

ORFPX32 Single-precision floating instruction ORFPX64 Double-precision floating instruction ORVDX64 Vector instruction

Table 4.1 Lists of RISC instruction set

4.2. The Proposed ISA

The proposed ISA has three major ideas: the input instructions, the block jump instruction and the output instructions.

4.2.1. Input Instructions

The purpose of the input instructions is to pass the value to OPENRISC. We choose the ori instruction (Format: ori rD,rA,K. The immediate value is zero-extended and combined with the contents of general-purpose register rA in a bit-wise logical OR operation. The result is placed into general-purpose register rD) and the movi instruction (Format: movhi rD,K.

The 16-bit immediate value is zero-extended, shifted left by 16 bits, and placed into general-purpose register rD.) to be input instruction.

Fig_4.2(a) and Fig. 4.2(b) show the machine code and the assembly code of the instruction. The memory stores the input instructions whose machine code are 0x198004d2 and 0xa98c162f. As the memory controller which is described in the section 3.3 reads instructions from memory, the memory controller detect the instruction whether the instruction is 0x198004d2 or 0xa98c162f. or not. If the instruction is 0x198004d2, the memory controller replaces the lower 16-bit part of the instruction to the higher 16-bit part of the instruction. Similarly, if the instruction is 0xa98c162f, the memory controller replaces the high 16-bit part of the instruction to the lower 16-bit part of the instruction. The above description shows in Fig. 4.3.

Fig. 4.2(a)

The input instruction of lower 16bits

Fig. 4.2(b)

The input instruction of higher 16bits

Fig. 4.3 The input instruction working flow

4.2.2. Block Jump Instruction

The instruction memory which is 256 x 32 bits is distributed into 16 blocks which consists of 16 32-bit instructions. We use the block to be a algorithm operation because most algorithm operation need less than 16 instructions.

The block jump instruction especially focuses on the clock phase issue whether REF_CLK is lead to DIV_CLK or not. Because the different issue has the different operation, we use the block jump instruction which shows in Fig. 4.4. If REF_CLK is lead to DIV_CLK and the memory controller reads the block jump instruction, the reading address is changed to the begin address of the num_block_read block. On the other hand, if REF_CLK is lag to DIV_CLK and the memory controller reads the block jump instruction, the reading address is changed to the begin address of the num_block_lag block. Fig. 4.5 shows the jumping process.

Jump_block, num_block_lag, num_block_lead

0

1c num_block_lag num_block_lead

31 26 25 8 7 4 3 0

Instruction format

machine code

Fig.4.4 The block jump instruction

Fig. 4.5 The working flow of the block jump instruciton

4.2.3. Output Instruction

The output instruction is the way of outputting the information of OPENRISC such as the DCO control word and the state control word. We choose the store instruction of ORBIS32. The store instruction has two parts to be information: data and address. Storing data is the DCO control word. Storing address is the state control word. Fig. 4.6 shows the machine code of the store instruction. Target Rf is a register which maintains the value of the DCO control word. Infor which is shown at Table 4.2 is the input of the state controller.

Fig. 4.6 The output instruction Infor Pin assignment State

0 Frequency Lock operation [0] DCO_mode

1 Phase Lock operation 0 Frequency detection [1] detect_mode

1 Phase Error detection 0 coarse tracking [2] Tracking_mode

1 fine tracking

Table 4.2 The pin assignment of the state controller

4.3. Proposed SDPLL Algorithm

The proposed SDPLL has two basic states: the coarse frequency state and the coarse phase state. At the coarse frequency state, we use the TDC to get the half value of the period of Ref_Clk. OPENRISC converts the proper value because of the different resolution between TDC and DCO. At the coarse phase state, the action shows in Fig. 4.7(a) and Fig.

4.7(b). We use the TDC to get the value of the phase error between Ref_Clk and Div_Clk . The memory controller jumps to the proper block according to lead and lag signal. We assumes the period of Ref_clk as A and the phase error is E. In the lead case which is shown in Fig. 4.7(a), DCO changes the period of Div_clk to A+E in order to lock the phase. On other hand, in the lead case which is shown in Fig. 4.7(b), DCO changes the period of

Fig. 4.7(a)

When Div_Clk is lead to Ref_Clk

Fig. 4.7(b)

When Div_Clk is lag to Ref_Clk

4.4. Simulation Result

Fig. 4.8 shows that the platform needs how many cycles to lock. The platform needs 3 cycles to lock frequency and 2.5 cycles to lock phase. Total cycle count to lock is 6. Fig. 4.9 (a) and Fig. 4.9 (b) show the waves of different clock period. Finally, we show comparison with other phase lock loops in Table 4.3.

Fig. 4.8 The cycle count of platform to lock

Fig. 4.9(a)The period of Ref_Clk is 6.3MHz

Fig. 4.9(b)The period of Ref_Clk is 50KHz

Performance Parameter

This work 06[2] ISSCC’04[3] JSSC’05[4]

Process 90nm CMOS 90nm CMOS 90nm CMOS 0.18um CMOS

Input Range 50KHz~6.3MHz 200KHz

~33MHz

30 KHz ~65 MHz

1KHz ~ 50MHz

Flexibility Yes No No No

Max Lock time 6 6 >150 <50

Table 4.3 Comparison with other phase lock loops

Chapter 5

Conclusion and Future Work

5.1. Conclusion

The proposed SDPLL has two levels for development. One is hardware system level which is comprised with ADPLL and OPENRISC. The other is the software level. The proposed SDPLL is flexible not only on the software level but also on hardware level. As the hardware upgrades, the proposed SDPLL just need to modify the software code. As a result, the proposed SDPLL can supply the flexible environment.

5.2. Future Work

The following topics to extend the work can be proposed.

I. The proposed SDPLL will combine the G.C.D (Greatest common divisor) application to recover NRZ (none return zero) clock signal.

II. The proposed SDPLL will lock the frequency-divided clock by more complicated instructions.

III. Enhancing the resolution of DCO and TDC is important issue.

References

[1] Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee” An all-digital phase-locked loop(ADPLL)-based clock recovery circuit” Solid-State Circuits, IEEE Journal of Volume 34, Issue 8, Aug. 1999 Page(s):1063-1073

[2]. Li Jyun-Rong, Hsu Terng-Yin” The Study of All Digital Phase-Locked Loop (ADPLL) and its Applications” Thesis CS, NCTU 2006.

[3]. J. Lin, B. Haroun, T. Foo, J.-S. Wang, b. Helmick, S. Randall, T. Mayhugh, C. Barr and J.

Kirkpartick, “A PVT Tolerant 0.18 MHz to 600 MHz Self-Calibrated Digital PLL in 90 nm CMOS Process, “ in Dig. Tech. Papers ISSCC＇04, Feb. 2004, pp. 488-489.

[4] Ching-Che Chung, Chen-Yi Lee, “An all-digital phase-locked loop for high-speed clock generation＂ IEEE Journal of Solid-State Circuits, Vol38,pp.347-351, Feb.2003

[6] “OpenRISC 1200 IP Core Specification” Rev. 0.7, Sep 6, 2001 [7] “OpenRISC 1000 Architecture Manual “July 13, 2004