Summary

We have introduced the functions and characters of each component above. We combine all components on ONU board and OLT board. The locations of all components on ONU board are shown as Fig. 4.5, and those on OLT board are shown as Fig. 4.6.

Fig. 4.5 Locations of All Components on ONU Board

Fig. 4.6 Locations of All Components on OLT Board

We illustrate the whole system of DHPON with simple a block diagram. The block diagram of DHPON system is shown as Fig. 4.7.

Figure 4.7 Block Diagram of DHPON System

In upstream, at the first, an Ethernet packet is transmitted from users to ONU Physical Layer. Then, an Ethernet packet is transmitted from ONU Physical Layer to FPGA with 4-bit parallel data at 25 MHz. Then a DHPON packet is transmitted from FPGA to Serdes with 16-bit parallel data at 77.76 MHz. Serdes transfers 16-bit parallel data to serial signal and then transmits serial signal to ONU Transceiver. ONU Transceiver sends the data to OLT Transceiver by the fiber. When OLT Transceiver receives the serial signal data, Serdes will transform the data into 16-bit parallel data at 77.76 MHz and then transmit the data with 16-bit parallel to FPGA. Last, FPGA transmits an Ethernet packet with 8-bit parallel data at 125 MHz to OLT Physical Layer. Then, the CO will get the Ethernet packet.

In downstream, at the first, an Ethernet packet is transmitted into OLT Physical Layer.

Then, an Ethernet packet is transmitted from OLT Physical Layer to FPGA with 8-bit parallel data at 125 MHz. The Ethernet packet is transmitted to Serdes by FPGA with 16-bit parallel data at 77.76 MHz. Serdes transfers 16-bit parallel data to serial signal and then transmits serial signal to OLT Transceiver. OLT Transceiver sends the data to ONU Transceiver by the fiber. When ONU Transceiver receives the serial signal, Serdes on ONU will transform the data into 16-bit parallel data at 77.76 MHz and then transmit the data with 16-bit parallel to FPGA. Last, FPGA transforms the data to an Ethernet packet and then transmits the Ethernet packet with 8-bit parallel data at 125 MHz to ONU Physical Layer. Then, the user will get the Ethernet packet.

CHAPTER 5

Testing and Results on Hardware

In this chapter, we will focus on testing of data traffic. We set up a DHPON system with one OLT to one ONU. It‘s shown as Fig. 5.1. Then, we will analyze the data on ONU board and OLT board.

Figure 5.1 Testing Architecture of DHPON

5.1 Testing Results of Data Traffic

We complete the system of DHPON, and transfer data between CO and Users. We will use EthView to generate Ethernet packets. EthView is software for analyzing and generating Ethernet packets. Then, Ethernet packets are send into DHPON network. We assign the module I/O pin to the test pins of the board, and the module I/O pin is on the inside of FPGA. We can use Logic-Analyzer (LA) to store and display the data which is on the inside of FPGA. Logic-Analyzer is an electronic instrument that displays signals in a digital circuit that are too fast to be observed and presents it to a user so that the user can more easily check correct operation of the digital system. Then, we can get the data more

easily by connecting the probes of Logic-Analyzer with the test pins of the board. That is shown in Fig. 5.2.

Figure 5.2 Connect Logic-Analyzer with the Board

I divide the system of DHPON into two parts, upstream and downstream parts, to analyze and explain the results.

5.1.1 Testing Results in Upstream

First, we use EthView to generate Ethernet packets, EthView is a software with Internet network. Then it sends the Ethernet packets to ONU by connecting ONU board with a computer through a Network-Line.

When the Ethernet packets pass PHY, they will be inputted to FPGA. The data is shown as Fig. 5.3. From the figure, we know that the data interface is 4-bits parallel data interface clocked at 25 MHz.

Figure 5.3 Inputs of FPGA on ONU Board

The output data of FPGA on ONU is shown as Fig. 5.4. From this figure, we know that these modules of ONU has divided the Ethernet packet into 268-bytes Payload, and added Header in front of Payload successfully. Through the process, the Ethernet packet becomes several 280-bytes DHPON packets. Fig. 5.5 shows that Header is added in front of Payload. From Fig. 5.5, we also know that the DHPON meets the data format of upstream and EOFB of the latest DHPON packet of an Ethernet packet is high. After PON packets pass SerDes and ONU Transceiver, we can send them to OLT by fiber with optical signals which is shown as Fig. 5.6.

Figure 5.4 DHPON Packets

Figure 5.5 Header of DHPON Packet

Figure 5.6 DHPON Packets with Optical Signal on Fiber

After OLT receives the data by the OLT Transceiver, the data is sent from SerDes to FPGA. on OLT. the it is shown as Fig. 5.7. Then PON Processor module will shift the data back to the right place and find ONU-ID and Payload-Length as Fig. 5.8 shows.

Other modules on OLT remove Header of DHPON packets and combine Payloads to form an Ethernet packet successfully. It is shown as Fig. 5.9. The Ethernet packet will be sent to PHY on OLT by FPGA. From Fig. 5.9, we know that the data interface meets the requirement of GMII. Fig. 5.10 shows the locations of gathering data (Fig. 5.3 ~ 5.9).

Figure 5.7 Input Data on OLT in Upstream

Figure 5.8 ONU-ID and Payload on OLT in Upstream

Figure 5.9 Output Packet on OLT in Upstream

Figure 5.10 Locations of Gathering Data in Upstream

5.1.2 Data Results in Downstream

The testing method of downstream is almost the same as the method of upstream. The only difference is that the Ethernet packets are sent to OLT by connecting OLT board with a computer through a Network-Line by EthView. As Fig. 5.11 shows, the input data of FPGA on OLT is an Ethernet packet. These modules of OLT will add Header in front of

Ethernet packets, and create a packet which meets the requirement of data format of Downstream. Then, FPGA send the packet to SerDes on OLT. The packet of downstream is shown as Fig. 5.12, and we know that the packet matches with the data format of downstream. OLT sent the packet of downstream to NOU by fiber with optical signal, and we show the signal as Fig. 5.13.

Figure 5.11 Inputs of FPGA on OLT

Figure 5.12 Packets of Downstream

Figure 5.13 Packets of Downstream on Fiber

After ONU receives the data by the ONU transceiver, the data is sent from SerDes to FPGA.. PON MAC module on ONU will shift the data to the right place and find out Payload-Length as Fig. 5.14 shows. Then, the modules of ONU will remove Header and construct an Ethernet packet successfully, and it is shown as Fig. 5.15. The Ethernet packet will be sent to PHY on OLT from FPGA. From Fig. 5.15, we know that the data interface matches with MII. Fig. 5.16 shows the locations of gathering data (Fig. 5.11 ~ 5.15).

Figure 5.14 Input Data of FPGA on ONU

Figure 5.15 Output Packet on ONU in Downstream

Figure 5.16 Locations of Gathering Data in Downstream

5.2 Testing Results of DHPON System

After we test Data Traffic of DHPON, we will test the performance, the efficiency and the work of our DHPON system.

5.2.1 Testing Results by SmartBits

First, we test the performance and efficiency of DHPON by SmartBits. SmartBits is a network performance testing equipment, which can generate, transmit, receive, analyze, and capture packets. The testing architecture is shown as Fig. 5.17. In downstream, we send the packets to OLT by SmartBits A, and receive the packets on ONU by SmartBits B.

In upstream, we send the packets to ONU by SmartBits B, and receive the packets on OLT by SmartBits A. Then we can calculate the efficiency of DHPON in downstream and upstream.

Figure 5.17 Testing Architecture by SmartBits 1. Transmitting 1,000,000 packets

We send 1,000,000 packets to OLT with 100 Mb/s speed in downstream, and receive on ONU by SmartBits B. On the other hand, we send 1,000,000 packets to ONU with 100 Mb/s speed in upstream, and receive on OLT by SmartBits A. All of packets by SmartBits sending out are random size and random background. The Result is shown as Fig. 5.18. In the Figure, we can know that SmartBits A receive 999,417 packets and SmartBits A receive 997,586 packets. So the efficiency in downstream is 99.94 %, and the efficiency in upstream is 99.76 %.

Figure 5.18 Results with Transmitting 1,000,000 packets 2. Transmitting 10,000,000 packets

We try transmitting more packets. This time, we send 10,000,000 packets to OLT and ONU with 100 Mb/s speed by SmartBits. The Result is shown as Fig. 5.19. In the Figure, we can know that SmartBits B receive 9,994,048 packets and SmartBits A receive 9.974,410 packets. So the efficiency in downstream is 99.94 %, and the efficiency in upstream is 99.7 4%.

Due to the result between two experiments is same, we can get that the DHPON is stable and the efficiency is almost perfect. Downstream efficiency DHPON is 99.95 %, and upstream efficiency DHPON is 99.75 %.

Figure 5.19 Results with Transmitting 10,000,000 packets

5.2.2 Testing Results by Video Streaming

We use VLC media player to generate a video streaming on the internet, then receive and display on a computer by our DHPON system. VLC media player is software with media player and streaming server. It can play various audio and video formats, also can be used as a server to generate video streaming stream on a high-bandwidth network.

We use VLC to generate a video streaming with Advanced Streaming Format (ASF) and 8 Mbps rate on network. As Fig. 5.20 , the two computers are connected by DHPON.

The player can play the Video Streaming smoothly with few Caches. This means the DHPON can transmit real-time data, and it can work.

Figure 5.20 DHPON with VLC

5.2.3 Testing Results by Remote Terminal

We use VNC (Virtual Network Computing) to test DHPON system with real-time data.

VNC is a remote desktop connection software, which allows you to view and fully interact with one computer desktop (the "VNC server") using a simple program (the "VNC viewer") on another computer desktop anywhere on the Internet, as Fig. 5.21 shows.

Figure 5.21 VNC System

If we replace the Internet with the DHPON system, as Fig. 5.22. VNC Server play a movie, then we watch the movie on VNC viewer which is one of the real-time data send by VNC server. As Fig. 5.23 shows, then the movie on VNC viewer will be played smoothly. It means DHPON can solve the problem that RTT is too long.

Figure 5.22 DHPON with VNC

Fig. 5.23 Testing Results by VNC

CHAPTER 6 Conclusion

The experiment of my part is the data traffic of OLT and ONU. I verify that by the EthView and LA, and the final result is exact. I calculate the efficiency in downstream and upstream by the SmartBits. In downstream, the efficiency is 99.9 %. In upstream, the efficiency is 99.7 %.

Figure 6.1 DHPON System

We have successfully set up a real DHPON system with an OLT and four ONUs, as Fig. 6.1. DHPON is based on the passive optical network and combined with TDM-PON, WDM-PON and Distributed control DBA to accomplish a passive optical network which

is high performance, shorter RTT, almost no packet delay, and simple structure. The high performance means bandwidth is not wasted and used effectively. The shorter RTT means the control message (Q-size of packet) can be updated immediately by distributed control DBA, therefore the packet delay problem is solved. In the end, we have proved that our DHPON can work exactly in the real work.

Reference

[1] Leonid G. Kazovsky, Wei-TaoShaw, David Gutierrez, Ning Cheng, and Shing-Wa Wong, ―Next-Generation Optical Access Networks,‖ Journal of Lightwave Technology, vol. 25, no. 11, pp. 3428 – 3442, November 2007.

[2] Ki-Man Choi, Sang-Mook Lee, Min-Hwan Kim, and Chang-Hee Lee, ―An Efficient Evolution Method From TDM-PON to Next-Generation PON,‖ IEEE Photonics Technology Letters, vol. 19, no. 9, pp. 647 -649, May 2007.

[3] Nicholas J. Frigo, Patrick P. Iannone, and Kenneth C. Reichmann ―A View of Fiber to the Home Economics,‖ IEEE Optical Communications, August 2004.

[4] Dawid Nowak, and John Murphy, ―FTTH：The Overview of Existing Technologies,‖

Opto-Ireland, 2005.

[5] G. Kramer, B. Mukherjee, and G. Pesavento, ―Ethernet PON (EPON)：Design and Analysis of an Optical Access Network,‖ Photonic Network Communications, vol. 3, no.3, pp. 307 – 319, July 2001.

[6] Soo-JinPark, Young-Bok Choi, Jung-Mi Oh, Sang-Geun Koo, and Donghan Lee,

―An Evolution Scenario of a Broadband Access Network Using R-SOA-Based WDM-PON Technologies,‖ Journal of Lightwave Technology, vol. 25, no. 11, pp.

3479 – 3487, November 2007.

[7] Jing Xie, Shengming Jiang, and Yuming Jiang, ―A Dynamic Bandwidth Allocation Scheme for Differentiated Service in EPONs,‖ IEEE Optical Communications, August 2004.

[8] Bart Lannoo, Lieven Verslegers, Didier Colle, Mario Pickavet, Maurice Gagnaire,

and Piet Demeester, ―Analytical model for the IPACT dynamic bandwidth allocation algorithm for EPONs,‖ Journal of Optical network, vol. 6, no. 6, pp. 677 – 688, June 2007.

[9] Sungkuen LEE, Eallae KIM, Yongwon LEE, Sangrok LEE, Daekwang JUNG, Seongtaek HWANG, Yunje OH, and Jinwoo PARK, ―A Design of WDM/TDM-PON Provisioning for Future Optical Access Network Upgrade,‖ Ieicetrans. Commun., vol. E90–B, no. 9, pp. 2456 – 2463, September 2007.

[10] Sherif R. Sherif, Antonis Hadjiantonis, Georgios Ellinas, Member,IEEE, Chadi Assi, and Mohamed A. Ali, ―A Novel Decentralized Ethernet-Based Passive Optical Network Architecture for Provisioning Differentiated QoS,‖ Journal of Lightwave Technology, vol. 22, no. 11, pp. 2483 – 2497, November 2004.

[11] Wikipedia, ―Gigabit Media Independent Interface,‖ http://en.wikipedia.org/wiki/

Gigabit_Media_Independent_Interface.

[12] Wikipedia, ―Media Independent Interface,‖ http://en.wikipedia.org/wiki/Media_Inde- pendent _Interface.

[13] Xilinx, ―Getting Started with FPGAs：What Are FPGAs？,‖ http://www.xilinx.com/

company/gettingstarted/index.htm.

[14] Xilinx, ―Getting Started with FPGAs：FPGA vs. ASIC,‖ http://www.xilinx.com/

company/gettingstarted/fpgavsasic.htm.

[15] J. Bhasker, ―Verilog HDL Synthesis, A Practical Primer,‖ http://www.amazon.com/

gp/reader/0965039153/ref=sib_fs_top/103-0861234-6092654?ie=UTF8&p=S00N&c heckSum=04EMRC4h8g%2BYJI2MqC4xIPVttBtjCWvv8N7yUhRhuw0%3D#