Disturb Characteristics

Chapter 3 The electrical characteristics of TFT flash memory

3.2 Disturb Characteristics

on, program disturbance, often takes place under the electrical stress applied to those neighbor

The first failure phenomen

ing un-programmed cells during programming a specific cell in the array. Two types of program disturbances, gate (word-line) disturbance and drain/source (bit-line) disturbance need to be considered. Fig. 2-3 shows the schematic circuitry of the memory array. During programming cell A, gate disturbance occurs in the cell B and those connected with the same word-line because the gate stress is applied to the same word-line (WL). Fig. 3-10 (a)-(c) show the gate disturb characteristics. After 1000s at 25°C, small extent of gate disturbance was found. During programming cell A, drain disturbance occurs in the cell C and those connected with the same bit-line because the drain stress is applied to the same bit-line (BL). Fig. 3-11 (a)-(c) show the drain disturb characteristics. After constant Vd stress1000s at 25°C and 85°C, we can find high voltage and high temperature stress resulting in a more terrible drain disturbance than low voltage and temperature stress.

This phenomenon is believed due to the presence of the localized traps along the grain boundaries in the channel, which can significantly affect the Vt shift through drain and gate bias stressing [10-11]. Therefore, to eliminate the traps along the grain boundaries in the channel is another key for achieving better performance. In addition, the read disturb characteristic is shown in Figs. 3-12 (a)-(c). For the cell reading, the unwanted electron injection would happen while the word-line voltage and bit-line voltage are under read operation. This phenomenon would result in a significant threshold voltage shift of our selected reading cell. However, the threshold voltage shift of the read disturbance was only 0.1V for all three samples after 1000s at 25°C as shown in Figs. 3-12 (a)-(c). This result means that the apparent read disturbance was not observed in our device. Because the gate voltage and drain voltage were different while the device was operated in program state and read state, respectively. The gate voltage and drain voltage for the reading operation are smaller than that in the program state. The gate voltage of the reading operation would not

induce in the serious grain boundaries trap and interface state trap. And so the read disturbance was not degraded as shown in Fig. 3-12 (a)-(c).

ig. 3-1 Cross-sectional HRTEM images of the gate stacks for the poly-Si TFT memories

with (a) HfO , (b) Hf silicate, and (c) Zr silicate trapping layers.

ig. 3-2 Diffraction patterns of (a)HfO2, (b)Hf silicate, and (c)Zr silicate trapping layers.

HfO and Hf silicate samples depict less degree of crystallization than Zr silicate.

HfO ₂ T-oxide 90A Lg=1µm

Fig. 3-3 (a) Ids-Vgs curves of the memory in the programmed/erased states for different programming conditions. The trapping layer is HfO2. The programming and erasing times are 1s. A memory window of larger than 5V can be achieved with Vg= Vd=13V programming condition.

HfSiO T-oxide 90A Lg=1µm

program Vg=Vd=10V program Vg=Vd=12V Erase

Id (A)

Fig. 3-3 (b) Ids-Vgs curves of the memory in the programmed/erased states for different programming conditions. The trapping layer is Hf-silicate. The programming and erasing times are 1s. A memory window of larger than 5V can be achieved with Vg=

Vd=12V programming condition.

ZrSiO T-oxide 90A Lg=1µm

Fig. 3-3 (c) Ids-Vgs curves of the memory in the programmed/erased states for different programming conditions. The trapping layer is Zr-silicate. The programming and erasing times are 1s. A memory window of larger than 5V can be achieved with Vg=

Vd=13V programming condition.

HfO2 T-oxide 90A Lg=1µm

Fig. 3-4 (a) Program and erase characteristics of poly-Si TFT memory with HfO2

trapping layer for different programming conditions. The programming time can be as short as 0.1ms if the window margin is set to 1V with Vg=Vd=10V. The erasing time is about 0.1 ms

HfSiO T-oxide 90A Lg=1µm

HfSiO Vg=Vd=8 Vs=0 HfSiO Vg=Vd=9 Vs=0 HfSiO Vg=Vd=10 Vs=0

Fig. 3-4 (b) Program and erase characteristics of poly-Si TFT memory with Hf-silicate trapping layer for different programming conditions. The programming time can be as short as 1ms if the window margin is set to 1V with Vg=Vd=10V. The erasing time is about 1 ms

ZrSiO T-oxide 90A Lg=1µm

ZrSiO Vg=Vd=8 Vs=0

ZrSiO Vg=Vd=9 Vs=0 ZrSiO Vg=Vd=10 Vs=0

Fig. 3-4 (c) Program and erase characteristics of poly-Si TFT memory with Zr-silicate trapping layer for different programming conditions. The programming time can be as short as 0.1ms if the window margin is set to 1V with Vg=Vd=10V. The erasing time is about 0.1 ms

Time(s)

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸

Charge loss (%)

0 20 40 60 80 100 120

HfO₂ t_ox 90A 25^oC HfO₂ t_ox 90A 85^oC

Fig. 3-5 (a) Data retention characteristics of poly-Si TFT memory with HfO2 trapping layer at T=25℃ and T=85℃.

Time(s)

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸

Charge loss (%)

0 20 40 60 80 100 120

Hf-silicate t_ox 90A 25^oC Hf-silicate t_ox 90A 85^oC

Fig. 3-5 (b) Data retention characteristics of poly-Si TFT memory with Hf-silicate apping layer at T=25℃ and T=85℃.

Time(s)

10

⁰

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

Charge loss

0 20 40 60 80 100 120

Zr-silicate t_ox 90A 25^oC Zr-silicate t_ox 90A 85^oC

Fig. 3-5 (c) Data retention characteristics of poly-Si TFT memory with Zr-silicate g layer at T=25℃ and T=85℃.

trappin

HfO2 t-oxide 90A Lg=1µm

PE cycles

10⁰ 10¹ 10² 10³ 10⁴ 10⁵

Vt (V)

2 4 6 8 10

E: Vg= -10V, Vd=10V, T=10ms P: Vg= 12V, Vd=12V, T=1ms

characteristics of HfO₂ poly-Si TFT memory. Memory window Fig. 3-6 (a) Endurance

narrows to about 2V after 10⁵ P/E cycles.

HfSiO t-oxide 90A Lg=1µm

PE cycles

10⁰ 10¹ 10² 10³ 10⁴ 10⁵

Vt (V)

0 2 4 6 8 10

E: Vg= -10V, Vd=10V, T=10ms P: Vg= 12V, Vd=12V, T=1ms

Fig 3-6 (b) Endurance characteristics of Hf-silicate poly-Si TFT memory. Memory window narrowing is less significant and the window is slightly lower than 4V after 10 5

P/E cycles.

ZrSiO t-oxide 90A Lg=1µm

PE cycles

10⁰ 10¹ 10² 10³ 10⁴ 10⁵

Vt (V)

0 2 4 6 8 10

E: Vg= -10V, Vd=10V, T=10ms P: Vg= 12V, Vd=12V, T=1ms

Fig 3-6 (c) Endurance characteristics of Zr-silicate poly-Si TFT memory. Memory window narrowing is less significant and the window is slightly lower than 4V after 10 5

P/E cycles.

T-oxide 90A retention cycling & fresh

Hf-silicate fresh 25

C Hf-silicate fresh 85

C

Hf-silicate after cycling 25

C Hf-silicate after cycling 85

C

Fig. 3-7 Data retention characteristics of poly-Si TFT memories with cycling an h

d fres at T=25℃ and T=85℃. The tunneling oxide thickness is 9nm, and trapping layer is Hf-silicat

T-oxide 200A retention cycling & fresh

Hf-silicate fresh 25

C Hf-silicate fresh 85

C

Hf-silicate after cycling 25

C Hf-silicate after cycling 85

C

Fig. 3-8 Data retention characteristics of poly-Si TFT memories with cycling and fresh

at T=25℃ and T=85℃. The tunneling oxide thickness is 20nm, and trapping layer is Hf-silica .

2-bits/cell operation

Forward read, Vd=1 E: Bit1, P: Bit2

Reverse read, Vs=1

Fig. 3-9 Demonstration of 2 bits/cell operation. E: erased; P: programmed; Bit1: drain side; Bit2: source side.

Table 1. Suggested bias conditions for the 2 bits/cell memory operation.

Program Erase Read

Vg 12 V -10 V 3 V Vd 12 V 10 V 0 V Bit1

Vs 0 V 0 V 1 V

Vg 12 V -10 V 3 V

Vd 0 V 0 V 1 V

Bit2

Vs 12 V 10 V 0 V

HfO ₂ T-Oxide 90A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt shift (V)

-1.0 -0.5 0.0 0.5 1.0

HfO2 Vg=10 Vd=Vs=0 HfO2 Vg=12 Vd=Vs=0

Fig. 3-10 (a) Programming gate disturb characteristics of HfO2 poly-Si TFT memory with different voltages.

HfSiO T-oxide 90A Lg=1µm

Stress Time(s)

1 10 100 1000

-1.0 -0.5 0.0 0.5 1.0

HfSiO Vg=10 Vd=Vs=0 HfSiO Vg=12 Vd=Vs=0

Vt shift (V)

Fig. 3-10 (b) Programming gate disturb characteristics of Hf-silicate poly-Si TFT memory with different voltages.

ZrSiO T-oxide 90A Lg=1µm

Stress Time (s)

1 10 100 1000 10000

Vt shift (V)

-1.5 -1.0 -0.5 0.0 0.5 1.0

ZrSiO Vg=10 Vd=Vs=0 ZrSiO Vg=12 Vd=Vs=0

Fig. 3-10 (c) Programming gate disturb characteristics of Zr-silicate poly-Si TFT memory with different voltages.

HfO2 T-oxide 90A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt shift (V)

-1 0 1 2

HfO2 Vd=10 Vg=Vs=0 25^oC HfO2 Vd=12 Vg=Vs=0 25^oC HfO2 Vd=10 Vg=Vs=0 85^oC HfO2 Vd=12 Vg=Vs=0 85^oC

Fig.3-11 (a) Drain disturb characteristics of HfO2 poly-Si TFT memory with different temperatures and voltages.

HfSiO T-oxide 90A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt shift (V)

-1 0 1

2 HfSiO Vd=10 Vg=Vs=0 25^oC HfSiO Vd=12 Vg=Vs=0 25^oC HfSiO Vd=10 Vg=Vs=0 85^oC HfSiO Vd=12 Vg=Vs=0 85^oC

Fig. 3-11 (b) Drain disturb characteristics of Hf-silicate poly-Si TFT memory with different temperatures and voltages.

ZrSiO T-oxide 90A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt shift (V)

-1 0 1

2 ZrSiO Vd=10 Vg=Vs=0 25^oC ZrSiO Vd=12 Vg=Vs=0 25^oC ZrSiO Vd=10 Vg=Vs=0 85^oC ZrSiO Vd=12 Vg=Vs=0 85^oC

Fig. 3-11 (c) Drain disturb characteristics of Zr-silicate poly-Si TFT memory with different temperatures and voltages.

HfO ₂ T-oxide 90A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt shift (V)

-1.0 -0.5 0.0 0.5 1.0

HfO2 Vg=3 Vd=1 Vs=0 HfO2 Vg=3 Vd=2 Vs=0

Fig. 3-12 (a) Read disturb characteristics of HfO2 poly-Si TFT memory with different read conditions at 25°C.

HfSiO T-oxide 90A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt shift (V)

-1.0 -0.5 0.0 0.5 1.0

HfSiO Vg=3 Vd=1 Vs=0 HfSiO Vg=3 Vd=2 Vs=0

Fig. 3-12 (b) Read disturb characteristics of Hf-silicate poly-Si TFT memory with different read conditions at 25°C

ZrSiO T-oxide 90A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt shift (V)

-1.0 -0.5 0.0 0.5 1.0

ZrSiO Vg=3 Vd=1 Vs=0 ZrSiO Vg=3 Vd=2 Vs=0

Fig. 3-12 (c) Read disturb characteristics of Zr-silicate poly-Si TFT memory with different read conditions at 25°C

Chapter 4 The electrical charact h different tunneling

4-1 Different tunneling oxide thickness

of the TFT flash memory device after NH3

plasm

eratu

eristics wit

oxide thickness and improvement of NH

₃

plasma treatment

Fig.4-1 (a)-(c) show the retention behavior

a treatment with different trapping layers (HfO₂, Hf-silicate, and Zr-silicate) in programmed state, at room temperature (25℃) and high temperature (85℃), respectively. As we mentioned above, the charge loss behavior under the high temp re condition is accelerated seriously than that under the room temperature condition. However, the device with thicker tunneling oxide thickness (20 nm) would have better retention performance than the sample with thinner tunneling oxide thickness (9 nm) as shown in Fig. 4-1 (a)-(c). In addition, the same tendency that the charge loss improved for the device with thicker tunneling oxide thickness was happened for the device with different trapping layers (HfO2, Hf-silicate, and Zr-silicate). It has been reputed that [12] the flash memory device with the thicker tunneling oxide thickness resulted in a worse performance during P/E speed.

Fortunately, this degradation of P/E speed for the different tunneling oxide thickness was not observed in our device as shown in Fig.4-2 (a)-(c). The reason for this phenomenon is the different way of the programming. For the sample with F-N programming [12], the thicker tunneling oxide thickness would have smaller electrical field resulted in the degradation of P/E speed. On the other hand, the device with channel hot electron programming would not degrade the P/E speed, resulting from the lucky electron of channel hot electron injection [13].

According to the lucky electron model of channel hot electron injection [13], the P(E_ox) were

the same order for the different tunneling oxide thickness with results in the devices with the different tunneling oxide thickness still have almost the same gate current. This reason explains why our device with thicker tunneling oxide thickness can a have better retention behavior while maintaining the P/E speed performance.

The characteristics of gate disturbance for the TFT flash memory devices after NH₃ plasma treatment with different trapping layers (HfO2, Hf-silicate, and Zr-silicate) and tunneling oxide thickness ( 20 nm & 9 nm) under different applied gate bias stress were shown in Fig.4-3 (a)-(c), respectively. As we can see in Fig.4-3 (a), the threshold voltage shift under 10 V applied gate voltage was smaller than the 12 V applied gate voltage for the device with 9 nm tunneling oxide. But this large Vt shift would much improved for the device with thicker tunneling oxide (20 nm) as shown in this figure. When the applied gate bias was 10 V, the threshold voltage shift was only about -0.2 V for the device with 20 nm tunneling oxide. The same trend was shown in all devices with different trapping layers (HfO₂, Hf-silicate, and Zr-silicate) as illustrated in Fig.4-3 (a)-(c). The reason for the improvement of gate disturbance for the device under different gate bias stress is the applied gate bias induced grain boundary trap [14] or interface state trap [14]. The gate disturbance can be affected by the grain boundary trap and the interface state trap. As the grain boundary trap and interface state trap increase, the gate disturbance would become more serious. Because of the threshold voltage was defined as gate voltage and would also been affected by the surface potential [14].

The surface potential would be larger for the device with the thinner gate oxide thickness than the device with the thicker gate oxide thickness resulted in the large trapping density while the applied gate voltage was the same value. In addition, the threshold voltage shift would also be more serious. This discussion can explain why the device with thicker tunneling oxide thickness would have better gate disturbance behavior. The same tendency was famed in all devices with different trapping layers (HfO₂, Hf-silicate, and Zr-silicate) as shown in Fig. 4-3 (a)-(c). Even the same trend happened in different trapping layers, the device with the HfO2

and Hf-silicate trapping layer exhibit the better gate disturbance performance as indicated in these three figures.

The drain disturbance behavior of the TFT flash memory device after NH₃ plasma treatment with different trapping layers (HfO2, Hf-silicate, and Zr-silicate) and tunneling oxide thickness ( 20 nm & 9 nm) under different applied gate bias stress were shown in Fig.4-4 (a)-(c), respectively. The drain disturbance was not serious in our samples as shown in these figures. The threshold voltage shift was only about 0.5 V for the devices with the HfO₂ and Hf-silicate trapping layer and 0.7 V for the device with Zr-silicate trapping layer, respectively. We can find that the different thickness of tunneling oxide thickness have no effect on the drain disturbance. But the applied drain bias significantly influenced the threshold voltage shift as indicated in these three figures. The Vt shift was increased with increasing of applied drain voltage stress. For the same tunneling oxide thickness, the threshold voltage shift under the low drain bias stress (10 V) was 0.25V smaller than that with the high drain bias stress (12 V). In addition, the same trend was found for all devices with different trapping layers as illustrated in Fig.4-4 (a)-(c).

4-2 Improvement of NH

plasma treatment

methods to improve the SiO2/poly-Si interf

The NH3 plasma treatment is one of the useful

ace and channel quality, resulting from the NH₃ plasma treatment can eliminate the trap density in both the SiO2/poly-Si interface and channel. Fig.4-5 shown the retention behavior of the TFT flash memory with and without NH₃ plasma treatment. As we can see in this figure, the device with NH3 plasma treatment had a better retention loss than the sample without NH₃ plasma treatment. Without the NH₃ plasma treatment, the charge loss of the sample with Hf-silicate trapping layer was loss more than 20% while the samples with HfO2

and Zr-silicate trapping layers were loss more than 40%. After the NH₃ plasma treatment, the charge loss of all the samples were much improved as shown in this figure. This result approved that the NH₃ plasma treatment was a very promising approach to improve the retention behavior of the TFT flash memory. In addition, the NH3 plasma treatment can improve the drain disturbance of the TFT flash memory device as indicated in Fig.4-6 (a)-(c).

These three figures compared the improvement of NH3 plasma treatment for the devices with different trapping layers (HfO₂, Hf-silicate, and Zr-silicate) and different tunneling oxide thickness. The NH3 plasma treatment can much reduced the Vt shift of the drain disturbance of the TFT flash memory with HfO₂ and Hf-silicate trapping layers to 0.5V. For the sample with Zr-silicate trapping layer, the Vt shift of the drain disturbance was about 0.6V. This is because the hydrogen atoms of NH₃ can terminate dangling bonds and replace weak bonds in the grain boundaries and SiO2/poly-Si interface and thus reduce the trap states in the poly-Si channel. To eliminate these trap states can improve both the performance and reliability of poly-Si TFTs. These results mean that the NH3 plasma treatment not only improves the data retention loss behavior but also the drain disturbance of the TFT flash memory.

Time(s)

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸

Charge loss (%)

0 20 40 60 80 100 120

HfO₂ t_ox 90A 25^oC HfO₂ t_ox 90A 85^oC HfO₂ t_ox 200A 25^oC HfO₂ t_ox 200A 85^oC

tion characteristics of HfO2 poly-Si TFT memory with different Fig. 4-1 (a) Data reten

tunneling oxide thickness at T=25℃ and T=85℃.

Time(s)

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸

Charge loss (%)

0 20 40 60 80 100 120

Hf-silicate t_ox 90A 25^oC Hf-silicate t_ox 90A 85^oC Hf-silicate t_ox 200A 25^oC Hf-silicate t_ox 200A 85^oC

ig. 4-1 (b) Data retention characteristics of Hf-silicate poly-Si TFT memory with F

different tunneling oxide thickness at T=25℃ and T=85℃.

Time(s)

10

⁰

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

Charge loss

0 20 40 60 80 100 120

Zr-silicate t_ox 90A 25^oC Zr-silicate t_ox 90A 85^oC Zr-silicate t_ox 200A 25^oC Zr-silicate t_ox 200A 85^oC

ig. 4-1 (c) Data retention characteristics of Zr-silicate poly-Si TFT memory with F

different tunneling oxide thickness at T=25℃ and T=85℃.

HfO ₂ T-oxide 200A Lg=1µm

HfO2 Vg=Vd=10 Vs=0 HfO2 Vg=Vd=9 Vs=0 HfO2 Vg=Vd=8 Vs=0

ig. 4-2 (a) Program and erase characteristics of HfO2 poly-Si TFT memory with F

tunneling oxide thickness 20nm for different programming conditions. The programming time can be as short as 1ms if the window margin is set to 1V with Vg=Vd=10V. The erasing time is about 1 ms.

HfSiO T-oxide 200A Lg=1µm

HfSiO Vg=Vd=10 Vs=0 HfSiO Vg=Vd=9 Vs=0 HfSiO Vg=Vd=8 Vs=0

HfSiO Vg= -10 Vd=10 Vs=0 HfSiO Vg= -9 Vd=9 Vs=0 HfSiO Vg= -8 Vd=8 Vs=0

ig. 4-2 (b) Program and erase characteristics of Hf-silicate poly-Si TFT memory with F

ZrSiO T-oxide 200A Lg=1µm

4 ZrSiO Vg=Vd=10 Vs=0 ZrSiO Vg=Vd=9 Vs=0 ZrSiO Vg=Vd=8 Vs=0

ZrSiO Vg= -10 Vd=10 Vs=0 ZrSiO Vg= -9 Vd=9 Vs=0 ZrSiO Vg= -8Vd=8 Vs=0

ig. 4-2 (c) Program and erase characteristics of Zr-silicate poly-Si TFT memory with F

tunneling oxide thickness 20nm for different programming conditions. The programming time can be as short as 1ms if the window margin is set to 1.5V with Vg=Vd=10V. The erasing time is about 1 ms.

Table 2. Comparison table for the HfO2, Hf-silicate and Zr-silicate poly-Si TFT

Tunneling oxide 9nm Tunneling oxide 20nm

memories in the aspects of tunneling oxide thickness 9nm and 20nm program speed. The program operation is Vg=10 V, Vd=10 V, and Vs=0. Those programming time are memory window at 1 V.

HfO

1×10

^-4

sec 1×10

^-3

sec

Hf-silicate 5×10

^-3

sec 1×10

^-3

sec

Zr-silicate 1 10

× ^-3

sec 1 10

× ^-3

sec

HfO ₂ T-Oxide 90A & 200A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt s hif t (V )

-1.0 -0.5 0.0 0.5 1.0

HfO2 tunneling oxide200A Vg=10 HfO2 tunneling oxide200A Vg=12 HfO2 tunneling oxide90A Vg=10 HfO2 tunneling oxide90A Vg=12

ig. 4-3 (a) Programming gate disturb characteristics of HfO2 poly-Si TFT memory with F

different tunneling oxide thickness and voltages.

HfSiO T-oxide 90A & 200A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt s hif t (V )

-1.0 -0.5 0.0 0.5 1.0

HfSiO tunneling oxide200A Vg=10 HfSiO tunneling oxide200A Vg=12 HfSiO tunneling oxide90A Vg=10 HfSiO tunneling oxide90A Vg=12

ig. 4-3 (b) Programming gate disturb characteristics of Hf-silicate poly-Si TFT memory F

with different tunneling oxide thickness and voltages.

ZrSiO T-oxide 90A & 200A Lg=1µm

Stress Time (s)

1 10 100 1000 10000

Vt s hif t (V )

-1.5 -1.0 -0.5 0.0 0.5 1.0

ZrSiO tunneling oxide200A Vg=10 ZrSiO tunneling oxide200A Vg=12 ZrSiO tunneling oxide90A Vg=10 ZrSiO tunneling oxide90A Vg=12

ig. 4-3 (c) Programming gate disturb characteristics of Zr-silicate poly-Si TFT memory F

with different tunneling oxide thickness and voltages.

HfO2 T-oxide 90A & 200A Lg=1µm

Stress Time (s)

1 10 100 1000

Vt shift (V)

-1 0 1 2

HfO2 tunneling oxide 90A Vd=10 HfO2 tunneling oxide 90A Vd=12 HfO2 tunneling oxide 200A Vd=10 HfO2 tunneling oxide 200A Vd=12

ig. 4-4 (a) Programming drain disturb characteristics of HfO2 poly-Si TFT memory F

with different tunneling oxide thickness and voltages.

HfSiO T-oxide 90A & 200 A Lg=1µm

Stress Time (s)

1 10 100 1000

V t shift (V)

-1 0 1 2

HfSiO tunneling oxide 90A Vd=10 HfSiO tunneling oxide 90A Vd=12 HfSiO tunneling oxide 200A Vd=10 HfSiO tunneling oxide 200A Vd=12

ig. 4-4 (b) Programming drain disturb characteristics of Hf-silicate poly-Si TFT F

memory with different tunneling oxide thickness and voltages.

ZrSiO T-oxide 90A & 200A Lg=1µm

Stress Time (s)

1 10 100 1000 10000

Vt s hif t (V )

-1.0 -0.5 0.0 0.5 1.0

ZrSiO tunneling oxide 90A Vd=10 ZrSiO tunneling oxide 90A Vd=12 ZrSiO tunneling oxide 200A Vd=10 ZrSiO tunneling oxide 200A Vd=12

ig. 4-4 (c) Programming drain disturb characteristics of Zr-silicate poly-Si TFT F

memory with different tunneling oxide thickness and voltages.

Time (s)

HfO2 NH₃ plasma treatment HfSiO fresh

HfSiO NH₃ plasma treatment ZrSiO fresh

ZrSiO NH₃ plasma treatment

ig. 4-5 The data retention behavior of the TFT flash memory with and without NH3

plasma treatment.

Drain disturb NH3 & fresh

Time (s)

1 10 100 1000 10000

Vt s hift (V)

-0.5 0.0 0.5 1.0 1.5 2.0

HfO2 t-oxide 200A NH₃Vd=12 HfO2 t-oxide 200A Vd=12 HfO2 t-oxide 90A NH₃Vd=12

ig. 4-6 (a) Programming drain disturb characteristics of HfO2 poly-Si TFT memory F

with different tunneling oxide thickness and NH3 plasma treatment.

Drain disturb NH3 & fresh

Time (s)

1 10 100 1000 10000

Vt s hift (V)

-0.5 0.0 0.5 1.0 1.5 2.0

HfSiO t-oxide 200A NH₃Vd=12 HfSiO t-oxide 200A Vd=12 HfSiO t-oxide 90A NH₃Vd=12

ig. 4-6 (b) Programming drain disturb characteristics of Hf-silicate poly-Si TFT F

memory with different tunneling oxide thickness and NH3 plasma treatment.

Drain disturb NH3 & fresh

Time (s)

1 10 100 1000 10000

Vt s hift (V)

-0.5 0.0 0.5 1.0 1.5 2.0

ZrSiO t-oxide 200A NH3 Vd=12 ZrSiO t-oxide 200A Vd=12

ZrSiO t-oxide 90A NH3Vd=12

ig. 4-6 (c) Programming drain disturb characteristics of Zr-silicate poly-Si TFT F

memory with different tunneling oxide thickness and NH3 plasma treatment.

Chapter 5 Conclusion

In this thesis, we have studied three kinds of high-k dielectrics, including HfO₂, Hf-silica

The TFT flash memory device with Zr-silicate trapping layer has a window of

(2) ₂

(3) e was also shown in the TFT flash memory device with

(4) emory device, the P/E

However the drain disturb and gate disturb are ories. Because

te and Zr-silicate as the trapping layer for the poly-Si TFT memory devices. By sticking with sufficiently low thermal-budget processing, we have successfully demonstrated the feasibility of fabricating nonvolatile poly-Si TFT flash memories with excellent characteristics ：

(1)

5 V while the applied gate bias at 12 V and applied drain bias at 12 V. This means the device in this experiment has a large memory window.

The TFT flash memory device with HfO trapping layer has a good

在文檔中高介電常數材料之低溫複晶矽快閃記憶體的研究 (頁 27-0)

Chapter 3 The electrical characteristics of TFT flash memory

3.2 Disturb Characteristics

HfO 2 T-oxide 90A Lg=1µm

HfSiO T-oxide 90A Lg=1µm

Id (A)

ZrSiO T-oxide 90A Lg=1µm

HfO2 T-oxide 90A Lg=1µm

HfSiO T-oxide 90A Lg=1µm

ZrSiO T-oxide 90A Lg=1µm

Time(s)

Charge loss (%)

Time(s)

Charge loss (%)

Time(s)

10

10

10

10

10

10

10

10

10

Charge loss

0 20 40 60 80 100 120

HfO2 t-oxide 90A Lg=1µm

PE cycles

Vt (V)

HfSiO t-oxide 90A Lg=1µm

PE cycles

Vt (V)

ZrSiO t-oxide 90A Lg=1µm

PE cycles

Vt (V)

T-oxide 90A retention cycling & fresh

Hf-silicate fresh 25

C Hf-silicate fresh 85

C

Hf-silicate after cycling 25

C Hf-silicate after cycling 85

C

T-oxide 200A retention cycling & fresh

Hf-silicate fresh 25

C Hf-silicate fresh 85

C

Hf-silicate after cycling 25

C Hf-silicate after cycling 85

C

2-bits/cell operation

Program Erase Read

Vg 12 V -10 V 3 V Vd 12 V 10 V 0 V Bit1

Vs 0 V 0 V 1 V

Vg 12 V -10 V 3 V

Vd 0 V 0 V 1 V

Bit2

Vs 12 V 10 V 0 V

HfO 2 T-Oxide 90A Lg=1µm

Stress Time (s)

Vt shift (V)

HfSiO T-oxide 90A Lg=1µm

Stress Time(s)

Vt shift (V)

ZrSiO T-oxide 90A Lg=1µm

Stress Time (s)

Vt shift (V)

HfO2 T-oxide 90A Lg=1µm

Stress Time (s)

Vt shift (V)

HfSiO T-oxide 90A Lg=1µm

Stress Time (s)

Vt shift (V)

ZrSiO T-oxide 90A Lg=1µm

Stress Time (s)

Vt shift (V)

HfO 2 T-oxide 90A Lg=1µm

Stress Time (s)

Vt shift (V)

HfSiO T-oxide 90A Lg=1µm

Stress Time (s)

HfO ₂ T-oxide 90A Lg=1µm

HfO ₂ T-Oxide 90A Lg=1µm

HfO ₂ T-oxide 90A Lg=1µm

HfO ₂ T-oxide 200A Lg=1µm

HfO ₂ T-Oxide 90A & 200A Lg=1µm