Things to Note in DSP Implementation
A.2 Emails Concerning Four DMA Channels and One DMA BusDMA Bus
“I’m a NCTU student using Quatro6x DSP board. Now, there are problems about DMA channels.
• Background:
There are four DMA channels at TMS320C6x01 DSP. There are four TMS320C6x01 on Quatro6x Board. TI’s on-chip memory: two blocks, four banks each. II’s dma copy mem, dma port to mem, and dma mem to port used for data movement.
• Goal:
We want to pipeline the five actions: one computing under background of four DMA channels moving data simultaneously.
• Status:
Up to now, it is OK to pipeline one CPU and one DMA using double buffering at
separate block. However, it is NG to pipeline one CPU and four DMA background movements simultaneously.
• Problem:
1) Could the four DMA channels move data simultaneously, or not?
2) If yes, how to do? Need to set data at separate bank?
3) Set by Data alignment or Structure for interleave LSB address?
4) If no, why could not? Limit from only one DMA controller having only one DMA bus?
5) Any suggestion for my goal in Q6x board?”
Reply from [email protected]
“I do not fully understand your problem. There are four DMA channels on each processor of the Q6x. Each processor is responsible for there own DMAs. DMA uses the same data bus as the processor so this is a time shared operation. If you have multiple DMA running they also time share the bus. The DMA when complete calls a DMA interrupt so you can use this to set flags and/or reset the DMA for new addresses. You can use the DMA with any of TI or II setup routines. If you have special needs then use the TI functions and if they have what you need then you will not have to build your own. At any time you can set the DMA for any special needs of data flow. We just give you the most common in the libraries. DSP0 does use one of the DMA channels for the BusMaster and this should not be changed unless you are not Busmastering data to or from the host.”
Reply from TI teacher George Hsieh
“DMA in ’C6x01 has only one controller and one 32-bit bus. Access priorities are fixed for each channel. Although you can pre-configure 4 different memory access configu-ration through 4 channels, only the highest priority channel can use the bus if started simultaneously, once this channel completes, the next highest priority channel would be-gin, and so on. If double buffer works for you, with a little modification, you can make
it as many buffer you want. Try to increase the frame count, and allocate more buffers as required, use frame and element index mechanism to direct the input to 4 different buffers, this can be done with only ONE channel of DMA. For details, please refer to the C6000 peripheral reference guide (SPRU190). It’s difficult to use DMA to move data in to/out from another DSP without a share memory. But simply for this case, I guess 3 channel will do, theoretically.”
Reply from [email protected]
“Thank you for contacting Texas Instruments Technical Support. Your email has been received and a case number 35347272 has been assigned to your inquiry. Regarding your query, it is not possible to have 4 DMA channels move data simultaneously. There is only one 32-bit DMA bus to the data access controller of C6201 which is the limitation. Please refer to figure 1-1 of SPRU577. Note that the 4 DMA channels have fixed priorities with channel 0 having highest priority and channel 3 having lowest priority. For more details on this please refer to section 2.7 of DMA Reference Guide - SPRU577. For your application, you can use Split-channel operation as described in section 2.6 of SPRU577. Also CPU and DMA has separate buses for memory and hence they can have simultaneous access.
Also refer to the following: Chapter 3 of SPRU577 TMS320C620x/TMS3206701 DMA and CPU: Data Access Performance - SPRA614A Hope this helps. Please get back to us if you have any further questions.”
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作者簡歷
李建興，民國五十九年生於台南市。民國八十四年畢業於國立台灣科技大學電 子系，民國八十八年進入國立交通大學電機資訊學院碩士在職專班電子與光電 組，民國九十三年取得碩士學位，論文題目為:在多數位訊號處理器系統上進行 高效率無線通道模擬之研討。